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Thu, 7 Sep 2023 15:20:22 +0000 To: CC: Subject: [PATCH v5 08/16] [gdb/aarch64] sve: Fix signal frame z/v register restore Date: Thu, 7 Sep 2023 16:20:10 +0100 Message-ID: <20230907152018.1031257-9-luis.machado@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230907152018.1031257-1-luis.machado@arm.com> References: <20230907152018.1031257-1-luis.machado@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT051:EE_|DB5PR08MB10046:EE_|AM7EUR03FT034:EE_|DB9PR08MB7584:EE_ X-MS-Office365-Filtering-Correlation-Id: 952eaca0-963c-4b93-f14e-08dbafb5faf8 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: I5VWM4IQasPXM5GQHzpEgDa611uNBaXv7USEv8DNmgqAQSKYJ6InsFM3N6bpxlpQwPc62U2cNi6Xjo5C7hPQRL/TbPoHLLEVoxFCaQi2J4h73WVWK932BPOJ1qqdEvrLuW02Pktb3qXSK4YNV7FXVEnyBsThFNS9YBRBRg/fbmGwAfuPIqCO1k8RR8uSPMm89oX1O2AEc9I5wr0g5AwNopKUMMWYYTmaOkpBmU8UxozkmSEq2ZYQ3kyaYAst2q/fwD0Cb4iReUIKeUm1LK44KAculJl5P6Jz6VqUtEjlOX/K2PStdePzknW1af8zjPR12elm0dlTSClXxN+hF3auPff6HJkAbRGva2Dv76LensA4dAoJGguKGdqATcsTDC1kbBo9YHz6OllHzX8Ro/tSoQ2/DuD2+M07KuZS2AenepY1IDC+Boo13mFMj7Bg2LymaoNnkMIgEEED1G/g5Smzh8+RehTlg7Z4EiPyh+9B5NopMg1pMjVoPUNoDGnzOl9o96uuiYwcPxGfcaEEkRJN6RotUbqD48O16M95IWEW2goP8NF5flhmZblJkWMJ24FeaGzsLiBqYhnmLRe7ShXXOSnCy8s7j2CwggGJy/Z9It8rgqjiZPIrEk/4hVUETukOhs8l49oPIuogqGhM/zulAd+874M0QHVU7G3XI1pDrgKXT+F26o/rZ4eByB1dPlXa5Lj8hjvoNQf8dcCTbKWivWKYNzB4rac5BHj2f+yanem0ZFGNtR/ZWHjfi9T62FhY X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT034.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB7584 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Luis Machado via Gdb-patches Reply-To: Luis Machado Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" While doing some SME work, I ran into the situation where the Z register contents restored from a signal frame are incorrect if the signal frame only contains fpsimd state and no sve state. This happens because we only restore the v register values in that case, and don't do anything for the z registers. Fix this by initializing the z registers to 0 and then copying over the overlapping part of the v registers to the z registers. While at it, refactor the code a bit to simplify it and make it smaller. Regression-tested on aarch64-linux Ubuntu 22.04/20.04. --- gdb/aarch64-linux-tdep.c | 107 +++++++++++++++++++++++---------------- 1 file changed, 62 insertions(+), 45 deletions(-) diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c index b183a3c9a38..bdd5cb05c10 100644 --- a/gdb/aarch64-linux-tdep.c +++ b/gdb/aarch64-linux-tdep.c @@ -196,14 +196,13 @@ read_aarch64_ctx (CORE_ADDR ctx_addr, enum bfd_endian byte_order, /* Given CACHE, use the trad_frame* functions to restore the FPSIMD registers from a signal frame. - VREG_NUM is the number of the V register being restored, OFFSET is the - address containing the register value, BYTE_ORDER is the endianness and - HAS_SVE tells us if we have a valid SVE context or not. */ + FPSIMD_CONTEXT is the address of the signal frame context containing FPSIMD + data. */ static void -aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs, - int vreg_num, CORE_ADDR offset, - enum bfd_endian byte_order, bool has_sve) +aarch64_linux_restore_vregs (struct gdbarch *gdbarch, + struct trad_frame_cache *cache, + CORE_ADDR fpsimd_context) { /* WARNING: SIMD state is laid out in memory in target-endian format. @@ -215,11 +214,22 @@ aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs, 2 - If the target is little endian, then SIMD state is little endian, so no byteswap is needed. */ - if (byte_order == BFD_ENDIAN_BIG) + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + int num_regs = gdbarch_num_regs (gdbarch); + aarch64_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + for (int i = 0; i < 32; i++) { + CORE_ADDR offset = (fpsimd_context + AARCH64_FPSIMD_V0_OFFSET + + (i * AARCH64_FPSIMD_VREG_SIZE)); + gdb_byte buf[V_REGISTER_SIZE]; - if (target_read_memory (offset, buf, V_REGISTER_SIZE) != 0) + /* Read the contents of the V register. */ + if (target_read_memory (offset, buf, V_REGISTER_SIZE)) + error (_("Failed to read fpsimd register from signal context.")); + + if (byte_order == BFD_ENDIAN_BIG) { size_t size = V_REGISTER_SIZE/2; @@ -234,50 +244,66 @@ aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs, store_unsigned_integer (buf + size , size, BFD_ENDIAN_LITTLE, u64); /* Now we can store the correct bytes for the V register. */ - trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + vreg_num, + trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + i, {buf, V_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_Q0_REGNUM - + vreg_num, {buf, Q_REGISTER_SIZE}); + + i, {buf, Q_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_D0_REGNUM - + vreg_num, {buf, D_REGISTER_SIZE}); + + i, {buf, D_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_S0_REGNUM - + vreg_num, {buf, S_REGISTER_SIZE}); + + i, {buf, S_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_H0_REGNUM - + vreg_num, {buf, H_REGISTER_SIZE}); + + i, {buf, H_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_B0_REGNUM - + vreg_num, {buf, B_REGISTER_SIZE}); + + i, {buf, B_REGISTER_SIZE}); - if (has_sve) + if (tdep->has_sve ()) trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_SVE_V0_REGNUM - + vreg_num, {buf, V_REGISTER_SIZE}); + + i, {buf, V_REGISTER_SIZE}); } - return; - } + else + { + /* Little endian, just point at the address containing the register + value. */ + trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + i, offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + i, + offset); - /* Little endian, just point at the address containing the register - value. */ - trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + vreg_num, offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + vreg_num, - offset); - - if (has_sve) - trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM - + vreg_num, offset); + if (tdep->has_sve ()) + trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM + + i, offset); + } + if (tdep->has_sve ()) + { + /* If SVE is supported for this target, zero out the Z + registers then copy the first 16 bytes of each of the V + registers to the associated Z register. Otherwise the Z + registers will contain uninitialized data. */ + std::vector z_buffer (tdep->vq * 16); + + /* We have already handled the endianness swap above, so we don't need + to worry about it here. */ + memcpy (z_buffer.data (), buf, V_REGISTER_SIZE); + trad_frame_set_reg_value_bytes (cache, + AARCH64_SVE_Z0_REGNUM + i, + z_buffer); + } + } } /* Implement the "init" method of struct tramp_frame. */ @@ -432,16 +458,7 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self, /* If there was no SVE section then set up the V registers. */ if (sve_regs == 0) - { - for (int i = 0; i < 32; i++) - { - CORE_ADDR offset = (fpsimd + AARCH64_FPSIMD_V0_OFFSET - + (i * AARCH64_FPSIMD_VREG_SIZE)); - - aarch64_linux_restore_vreg (this_cache, num_regs, i, offset, - byte_order, tdep->has_sve ()); - } - } + aarch64_linux_restore_vregs (gdbarch, this_cache, fpsimd); } trad_frame_set_id (this_cache, frame_id_build (sp, func)); -- 2.25.1