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Thu, 7 Sep 2023 15:20:23 +0000 To: CC: Subject: [PATCH v5 13/16] [gdb/generic] corefile/bug: Fixup (gcore) core file target description reading order Date: Thu, 7 Sep 2023 16:20:15 +0100 Message-ID: <20230907152018.1031257-14-luis.machado@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230907152018.1031257-1-luis.machado@arm.com> References: <20230907152018.1031257-1-luis.machado@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT011:EE_|PAVPR08MB8845:EE_|AM7EUR03FT058:EE_|GVXPR08MB7896:EE_ X-MS-Office365-Filtering-Correlation-Id: 1acca29c-3844-4d8d-ce71-08dbafb5fad2 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 4mAfPgVr+hqw96hHeX0gjDVTo1DG2KJdlXTbzYaUbDLP/f7d3ujREyRBNBZvAIOfk+Ks/WMcQdnYjPKed3jGfc4BL8Dj+SRV/vEUP1fZmmHU5uy6JYGRUcE5nveE4G/8JXLXvhSiy/HP65BUlna9RojGwVfkZy4ocIdoAymO83VSzJ7UQUljuKxIpTkm3DYg5dxcrkFciR9+g4GmS9mD+JpWNZAdKt8XL+8eZbgO60lPwiim7X0jRZfBt+W2ycxMBfF00zlo/zKdgOmje7J2QGHrXCEeNUpyOMuwpbhqbvsoqvPxSLppFyM1aqzhRfmrdMdbn9ThrF+BCpAD2SMe2xFnaWYKL7mKTVGASIIXuNOgn/5pCknv+gbovz7e1l8J6H57APwn4e9UZ7WGGRPO/mAHhnhTfMUpB6g6oI5x2fzKLrhj0bGKU6gKYm5ckbV3n4vJ5ILGZo52pkTjdKh3RdSpL461BFmivCPjET0MnhpVAhT+czKLUShkyzL7aaUH9WcWU2tAxWi7wE7Bt4ndUu09aP0JaOTNz7oMdlrMkapSfz/n7rxVbfkl/xlc6wfVhaQ+5rpb/vD8qoUZcaw0LtgEiH3gcH6NLFhayep3w1GBzQne1pRLVB8m1TC66LHhPZ+tLTQyRvWX7G1xTw75KqMQICGXoxQYNbTyU7TPo/sVWXO1+y9zUJzTNJx7ScDO+iATpAzk+HAAkaPWDfMb/iK4rcqeD6CO+aH919/gRxr1N/WnVTDBQmKMLqHRACU2pABBaNsol+ANUG6zR90eHiOvNj8aUCCUbHa/hQIbBZI= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT058.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR08MB7896 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Luis Machado via Gdb-patches Reply-To: Luis Machado Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" Due to the nature of the AArch64 SVE/SME extensions in GDB, each thread can potentially have distinct target descriptions/gdbarches. When loading a gcore-generated core file, at the moment GDB gives priority to the target description dumped to NT_GDB_TDESC. Though technically correct for most target, it doesn't work correctly for AArch64 with SVE or SME support. The correct approach for AArch64/Linux is to rely on the gdbarch_core_read_description hook, so it can figure out the proper target description for a given thread based on the various available register notes. I think this should work for other architectures as well. If not, we may need to adjust things so all architectures get the information that they need for discovering the target description of the core file. Regression-tested on aarch64-linux Ubuntu 22.04/20.04. --- gdb/corelow.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/gdb/corelow.c b/gdb/corelow.c index 439270f5559..ae1641fe5d2 100644 --- a/gdb/corelow.c +++ b/gdb/corelow.c @@ -1229,6 +1229,21 @@ core_target::thread_alive (ptid_t ptid) const struct target_desc * core_target::read_description () { + /* If the architecture provides a corefile target description hook, use + it now. Even if the core file contains a target description in a note + section, it is not useful for targets that can potentially have distinct + descriptions for each thread. One example is AArch64's SVE/SME + extensions that allow per-thread vector length changes, resulting in + registers with different sizes. */ + if (m_core_gdbarch && gdbarch_core_read_description_p (m_core_gdbarch)) + { + const struct target_desc *result; + + result = gdbarch_core_read_description (m_core_gdbarch, this, core_bfd); + if (result != nullptr) + return result; + } + /* If the core file contains a target description note then we will use that in preference to anything else. */ bfd_size_type tdesc_note_size = 0; @@ -1252,15 +1267,6 @@ core_target::read_description () } } - if (m_core_gdbarch && gdbarch_core_read_description_p (m_core_gdbarch)) - { - const struct target_desc *result; - - result = gdbarch_core_read_description (m_core_gdbarch, this, core_bfd); - if (result != NULL) - return result; - } - return this->beneath ()->read_description (); } -- 2.25.1