[PATCH 12/20] sim: microblaze: move arch-specific settings to internal header

Mike Frysinger via Gdb-patches
2022-12-23T06:09:28Z

with common/ sim code, so move it all out to a new header which only
this port will include.
---
sim/microblaze/interp.c | 1 +
sim/microblaze/microblaze-sim.h | 46 +++++++++++++++++++++++++++++++++
sim/microblaze/sim-main.h | 24 -----------------
3 files changed, 47 insertions(+), 24 deletions(-)
create mode 100644 sim/microblaze/microblaze-sim.h

diff --git a/sim/microblaze/interp.c b/sim/microblaze/interp.c
index 3d7fde0af3e3..8a8cb9f2b832 100644
--- a/sim/microblaze/interp.c
+++ b/sim/microblaze/interp.c
@@ -33,6 +33,7 @@
#include "sim-signal.h"
#include "sim-syscall.h"

+#include "microblaze-sim.h"
#include "microblaze-dis.h"

#define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
diff --git a/sim/microblaze/microblaze-sim.h b/sim/microblaze/microblaze-sim.h
new file mode 100644
index 000000000000..9e5fb0711c58
--- /dev/null
+++ b/sim/microblaze/microblaze-sim.h
@@ -0,0 +1,46 @@
+/* Copyright 2009-2022 Free Software Foundation, Inc.
+
+ This file is part of the Xilinx MicroBlaze simulator.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef MICROBLAZE_SIM_H
+#define MICROBLAZE_SIM_H
+
+#include "microblaze.h"
+
+/* The machine state.
+ This state is maintained in host byte order. The
+ fetch/store register functions must translate between host
+ byte order and the target processor byte order.
+ Keeping this data in target byte order simplifies the register
+ read/write functions. Keeping this data in native order improves
+ the performance of the simulator. Simulation speed is deemed more
+ important. */
+
+/* The ordering of the microblaze_regset structure is matched in the
+ gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro. */
+ struct microblaze_regset
+{
+ signed_4 regs[32]; /* primary registers */
+ signed_4 spregs[2]; /* pc + msr */
+ int cycles;
+ int insts;
+ unsigned_1 imm_enable;
+ signed_2 imm_high;
+};
+
+#define MICROBLAZE_SIM_CPU(cpu) ((struct microblaze_regset *) CPU_ARCH_DATA (cpu))
+
+#endif /* MICROBLAZE_SIM_H */
diff --git a/sim/microblaze/sim-main.h b/sim/microblaze/sim-main.h
index 160f10156fff..7646dad044fe 100644
--- a/sim/microblaze/sim-main.h
+++ b/sim/microblaze/sim-main.h
@@ -18,31 +18,7 @@
#ifndef MICROBLAZE_SIM_MAIN
#define MICROBLAZE_SIM_MAIN

-#include "microblaze.h"
#include "sim-basics.h"
#include "sim-base.h"

-/* The machine state.
- This state is maintained in host byte order. The
- fetch/store register functions must translate between host
- byte order and the target processor byte order.
- Keeping this data in target byte order simplifies the register
- read/write functions. Keeping this data in native order improves
- the performance of the simulator. Simulation speed is deemed more
- important. */
-
-/* The ordering of the microblaze_regset structure is matched in the
- gdb/config/microblaze/tm-microblaze.h file in the REGISTER_NAMES macro. */
- struct microblaze_regset
-{
- signed_4 regs[32]; /* primary registers */
- signed_4 spregs[2]; /* pc + msr */
- int cycles;
- int insts;
- unsigned_1 imm_enable;
- signed_2 imm_high;
-};
-
-#define MICROBLAZE_SIM_CPU(cpu) ((struct microblaze_regset *) CPU_ARCH_DATA (cpu))
-
#endif /* MICROBLAZE_SIM_MAIN */
--
2.39.0