[PATCH 16/20] sim: mcore: move arch-specific settings to internal header

Mike Frysinger via Gdb-patches
2022-12-23T06:10:25Z

with common/ sim code, so move it all out to a new header which only
this port will include.
---
sim/mcore/interp.c | 2 ++
sim/mcore/mcore-sim.h | 64 +++++++++++++++++++++++++++++++++++++++++++
sim/mcore/sim-main.h | 40 ---------------------------
3 files changed, 66 insertions(+), 40 deletions(-)
create mode 100644 sim/mcore/mcore-sim.h

diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c
index 8465f56d2d7c..84b243f07059 100644
--- a/sim/mcore/interp.c
+++ b/sim/mcore/interp.c
@@ -38,6 +38,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */

#include "target-newlib-syscall.h"

+#include "mcore-sim.h"
+
#define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)

diff --git a/sim/mcore/mcore-sim.h b/sim/mcore/mcore-sim.h
new file mode 100644
index 000000000000..239a079ebb3a
--- /dev/null
+++ b/sim/mcore/mcore-sim.h
@@ -0,0 +1,64 @@
+/* Simulator for Motorola's MCore processor
+ Copyright (C) 2009-2022 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef MCORE_SIM_H
+#define MCORE_SIM_H
+
+#include <stdint.h>
+
+/* The machine state.
+ This state is maintained in host byte order. The
+ fetch/store register functions must translate between host
+ byte order and the target processor byte order.
+ Keeping this data in target byte order simplifies the register
+ read/write functions. Keeping this data in native order improves
+ the performance of the simulator. Simulation speed is deemed more
+ important. */
+
+/* The ordering of the mcore_regset structure is matched in the
+ gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
+struct mcore_regset
+{
+ int32_t gregs[16]; /* primary registers */
+ int32_t alt_gregs[16]; /* alt register file */
+ int32_t cregs[32]; /* control registers */
+ int32_t pc;
+};
+#define LAST_VALID_CREG 32 /* only 0..12 implemented */
+#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
+
+struct mcore_sim_cpu {
+ union
+ {
+ struct mcore_regset regs;
+ /* Used by the fetch/store reg helpers to access registers linearly. */
+ int32_t asints[NUM_MCORE_REGS];
+ };
+
+ /* Used to switch between gregs/alt_gregs based on the control state. */
+ int32_t *active_gregs;
+
+ int ticks;
+ int stalls;
+ int cycles;
+ int insts;
+};
+
+#define MCORE_SIM_CPU(cpu) ((struct mcore_sim_cpu *) CPU_ARCH_DATA (cpu))
+
+#endif
diff --git a/sim/mcore/sim-main.h b/sim/mcore/sim-main.h
index 684ec39354be..fc48834feb45 100644
--- a/sim/mcore/sim-main.h
+++ b/sim/mcore/sim-main.h
@@ -22,45 +22,5 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "sim-basics.h"
#include "sim-base.h"

-/* The machine state.
- This state is maintained in host byte order. The
- fetch/store register functions must translate between host
- byte order and the target processor byte order.
- Keeping this data in target byte order simplifies the register
- read/write functions. Keeping this data in native order improves
- the performance of the simulator. Simulation speed is deemed more
- important. */
-
-/* The ordering of the mcore_regset structure is matched in the
- gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
-struct mcore_regset
-{
- int32_t gregs[16]; /* primary registers */
- int32_t alt_gregs[16]; /* alt register file */
- int32_t cregs[32]; /* control registers */
- int32_t pc;
-};
-#define LAST_VALID_CREG 32 /* only 0..12 implemented */
-#define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
-
-struct mcore_sim_cpu {
- union
- {
- struct mcore_regset regs;
- /* Used by the fetch/store reg helpers to access registers linearly. */
- int32_t asints[NUM_MCORE_REGS];
- };
-
- /* Used to switch between gregs/alt_gregs based on the control state. */
- int32_t *active_gregs;
-
- int ticks;
- int stalls;
- int cycles;
- int insts;
-};
-
-#define MCORE_SIM_CPU(cpu) ((struct mcore_sim_cpu *) CPU_ARCH_DATA (cpu))
-
#endif

--
2.39.0