From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id o5SON+TXR2NhkwsAWB0awg (envelope-from ) for ; Thu, 13 Oct 2022 05:18:28 -0400 Received: by simark.ca (Postfix, from userid 112) id D43E31E112; Thu, 13 Oct 2022 05:18:28 -0400 (EDT) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=JrFDHll5; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-3.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 741091E0CB for ; Thu, 13 Oct 2022 05:18:28 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 03F6A384B402 for ; Thu, 13 Oct 2022 09:18:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 03F6A384B402 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665652708; bh=RzpMqSfYHWprMjeEzcndetYMu6sM1L0C3BBJnE+Bxcc=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=JrFDHll5ksEEZs3xXLK9Oj16YpiN94nDs1f6cAP6ETChm8cKKJSMEaarbAzT3W6Hi sqdlG54dkfOfkhNxrDLsxQcDJGVKwv/PCXuPt2J/4UMQAkGr+BxKEqJ7ZtlKzB3Zk/ kZ8oYJ8VV0FhlaBI8nbE5CqWrJxoTE+7GQa2pyvM= Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by sourceware.org (Postfix) with ESMTPS id EE22A385020E for ; Thu, 13 Oct 2022 09:18:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EE22A385020E Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29D8wWhF022068; Thu, 13 Oct 2022 11:18:05 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3k64m7m4xy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Oct 2022 11:18:05 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 215A5100034; Thu, 13 Oct 2022 11:18:00 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id ECBBE21B535; Thu, 13 Oct 2022 11:18:00 +0200 (CEST) Received: from jkgcxl0002.jkg.st.com (10.75.127.122) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2375.31; Thu, 13 Oct 2022 11:17:59 +0200 To: Subject: [PATCH v2] gdb/arm: Stop unwinding on error, but do not assert Date: Thu, 13 Oct 2022 11:17:41 +0200 Message-ID: <20221013091740.645783-1-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.75.127.122] X-ClientProxiedBy: GPXDAG2NODE4.st.com (10.75.127.68) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-13_06,2022-10-12_01,2022-06-22_01 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: =?utf-8?q?Torbj=C3=B6rn_SVENSSON_via_Gdb-patches?= Reply-To: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" When it's impossible to read the FPCCR and XPSR, the unwinding is unpredictable as the it's not possible to determine the correct frame size or padding. The only sane thing to do in this condition is to stop the unwinding. Without this patch, gdb would assert if this errornous state was detected. Signed-off-by: Torbjörn SVENSSON --- gdb/arm-tdep.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 041e6afefed..afcbce478c2 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3591,9 +3591,13 @@ arm_m_exception_cache (frame_info_ptr this_frame) ULONGEST fpcar; /* Read FPCCR register. */ - gdb_assert (safe_read_memory_unsigned_integer (FPCCR, - ARM_INT_REGISTER_SIZE, - byte_order, &fpccr)); + if (!safe_read_memory_unsigned_integer (FPCCR, ARM_INT_REGISTER_SIZE, + byte_order, &fpccr)) + { + warning (_("Could not fetch required FPCCR content. Further " + "unwind is impossible.")); + return NULL; + } /* Read FPCAR register. */ if (!safe_read_memory_unsigned_integer (FPCAR, ARM_INT_REGISTER_SIZE, @@ -3669,9 +3673,15 @@ arm_m_exception_cache (frame_info_ptr this_frame) aligner between the top of the 32-byte stack frame and the previous context's stack pointer. */ ULONGEST xpsr; - gdb_assert (safe_read_memory_unsigned_integer (cache->saved_regs[ - ARM_PS_REGNUM].addr (), 4, - byte_order, &xpsr)); + if (!safe_read_memory_unsigned_integer (cache->saved_regs[ARM_PS_REGNUM] + .addr (), ARM_INT_REGISTER_SIZE, + byte_order, &xpsr)) + { + warning (_("Could not fetch required XPSR content. Further unwind " + "is impossible.")); + return NULL; + } + if (bit (xpsr, 9) != 0) { CORE_ADDR new_sp = arm_cache_get_prev_sp_value (cache, tdep) + 4; @@ -3703,6 +3713,14 @@ arm_m_exception_this_id (frame_info_ptr this_frame, *this_cache = arm_m_exception_cache (this_frame); cache = (struct arm_prologue_cache *) *this_cache; + /* Unwind of this frame is not possible. Return outer_frame_id to stop the + unwinding. */ + if (cache == NULL) + { + *this_id = outer_frame_id; + return; + } + /* Our frame ID for a stub frame is the current SP and LR. */ arm_gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); @@ -3725,6 +3743,11 @@ arm_m_exception_prev_register (frame_info_ptr this_frame, *this_cache = arm_m_exception_cache (this_frame); cache = (struct arm_prologue_cache *) *this_cache; + /* It's not allowed to call prev_register when this_id has returned the + outer_frame_id. The arm_m_exception_cache function will return NULL when + the frame cannot be properly unwinded. */ + gdb_assert (cache != NULL); + /* The value was already reconstructed into PREV_SP. */ arm_gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); -- 2.25.1