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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230016)(4636009)(346002)(376002)(39860400002)(396003)(136003)(40470700004)(36840700001)(46966006)(40480700001)(4326008)(8676002)(44832011)(2906002)(70586007)(70206006)(316002)(966005)(478600001)(36756003)(82310400005)(6916009)(54906003)(41300700001)(7696005)(86362001)(26005)(36860700001)(81166007)(8936002)(5660300002)(82740400003)(1076003)(107886003)(336012)(426003)(47076005)(186003)(2616005)(83380400001)(40460700003); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2022 10:15:16.3882 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95e2ffc0-b737-4284-fec4-08da7926e3dc X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT011.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR08MB5339 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Luis Machado via Gdb-patches Reply-To: Luis Machado Cc: mark@klomp.org Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" The arm record tests handle 16-bit and 32-bit thumb instructions, but the code is laid out in a way that handles the 32-bit thumb instructions as two 16-bit parts. This is fine, but it is prone to host-endianness issues given how the two 16-bit parts are stored and how they are accessed later on. Arm is little-endian by default, so running this test with a GDB built with --enable-targets=all and on a big endian host will run into the following: Running selftest arm-record. Process record and replay target doesn't support syscall number -2036195 Process record does not support instruction 0x7f70ee1d at address 0x0. Self test failed: self-test failed at ../../binutils-gdb/gdb/arm-tdep.c:14482 Investigating this a bit further, there seems to be a chance to do a simple fix through a type template, using uint16_t for 16-bit thumb instructions and uint32_t for 32-bit thumb instructions. This patch implements this. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29432 --- gdb/arm-tdep.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index cf8b610a381..57b865a0819 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -14387,14 +14387,18 @@ decode_insn (abstract_memory_reader &reader, #if GDB_SELF_TEST namespace selftests { -/* Provide both 16-bit and 32-bit thumb instructions. */ +/* Provide both 16-bit and 32-bit thumb instructions. + For 16-bit Thumb instructions, an array of uint16_t should be used. + For 32-bit Thumb instructions, an array of uint32_t should be used. */ + +template class instruction_reader_thumb : public abstract_memory_reader { public: template instruction_reader_thumb (enum bfd_endian endian, - const uint16_t (&insns)[SIZE]) + const T (&insns)[SIZE]) : m_endian (endian), m_insns (insns), m_insns_size (SIZE) {} @@ -14404,18 +14408,14 @@ class instruction_reader_thumb : public abstract_memory_reader SELF_CHECK (memaddr % 2 == 0); SELF_CHECK ((memaddr / 2) < m_insns_size); - store_unsigned_integer (buf, 2, m_endian, m_insns[memaddr / 2]); - if (len == 4) - { - store_unsigned_integer (&buf[2], 2, m_endian, - m_insns[memaddr / 2 + 1]); - } + store_unsigned_integer (buf, sizeof (T), m_endian, m_insns[memaddr / 2]); + return true; } private: enum bfd_endian m_endian; - const uint16_t *m_insns; + const T *m_insns; size_t m_insns_size; }; @@ -14436,6 +14436,8 @@ arm_record_test (void) memset (&arm_record, 0, sizeof (arm_insn_decode_record)); arm_record.gdbarch = gdbarch; + /* Use the endian-free representation of the instructions here. The test + will handle endianness conversions. */ static const uint16_t insns[] = { /* db b2 uxtb r3, r3 */ 0xb2db, @@ -14444,7 +14446,7 @@ arm_record_test (void) }; enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); - instruction_reader_thumb reader (endian, insns); + instruction_reader_thumb reader (endian, insns); int ret = decode_insn (reader, &arm_record, THUMB_RECORD, THUMB_INSN_SIZE_BYTES); @@ -14470,13 +14472,15 @@ arm_record_test (void) memset (&arm_record, 0, sizeof (arm_insn_decode_record)); arm_record.gdbarch = gdbarch; - static const uint16_t insns[] = { - /* 1d ee 70 7f mrc 15, 0, r7, cr13, cr0, {3} */ - 0xee1d, 0x7f70, + /* Use the endian-free representation of the instruction here. The test + will handle endianness conversions. */ + static const uint32_t insns[] = { + /* mrc 15, 0, r7, cr13, cr0, {3} */ + 0x7f70ee1d, }; enum bfd_endian endian = gdbarch_byte_order_for_code (arm_record.gdbarch); - instruction_reader_thumb reader (endian, insns); + instruction_reader_thumb reader (endian, insns); int ret = decode_insn (reader, &arm_record, THUMB2_RECORD, THUMB2_INSN_SIZE_BYTES); -- 2.25.1