From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id 6OOJJC0952IKJh4AWB0awg (envelope-from ) for ; Sun, 31 Jul 2022 22:40:45 -0400 Received: by simark.ca (Postfix, from userid 112) id 7F1601EA05; Sun, 31 Jul 2022 22:40:45 -0400 (EDT) Authentication-Results: simark.ca; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=OGazzcNR; dkim-atps=neutral X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-3.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 9A75D1E9ED for ; Sun, 31 Jul 2022 22:40:44 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 06499385802E for ; Mon, 1 Aug 2022 02:40:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 06499385802E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1659321644; bh=jpiipeOpcM8yUwHPIsM35Sgmwk0lI57iHWLgXi+h1XY=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=OGazzcNR+MslpltOKkIU0OqGy3J5g0GRFjM0j78w/ioXSIbqhaaH8ErMj3CBYV0HR tlJXtI11obv+bXwEJHQKdHJpH6M2eZt+RguiEtsDtaxJfnrnJfLuHUYAdKgznsLURr STtJg/OrIXOWctx02cT2MFN3+ky3awXFbukPDN4I= Received: from out30-131.freemail.mail.aliyun.com (out30-131.freemail.mail.aliyun.com [115.124.30.131]) by sourceware.org (Postfix) with ESMTPS id E82393858412 for ; Mon, 1 Aug 2022 02:40:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E82393858412 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R151e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045176; MF=jiangshuai_li@linux.alibaba.com; NM=1; PH=DS; RN=2; SR=0; TI=SMTPD_---0VL-P2iL_1659321620; Received: from lijsh-VirtualBox.hz.ali.com(mailfrom:jiangshuai_li@linux.alibaba.com fp:SMTPD_---0VL-P2iL_1659321620) by smtp.aliyun-inc.com; Mon, 01 Aug 2022 10:40:21 +0800 To: gdb-patches@sourceware.org Subject: [PATCH v3] gdb/csky support .reg2 for kernel 4.x and later Date: Mon, 1 Aug 2022 10:40:15 +0800 Message-Id: <20220801024015.3704-1-jiangshuai_li@linux.alibaba.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Jiangshuai Li via Gdb-patches Reply-To: Jiangshuai Li Cc: Jiangshuai Li Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" When kernel's version >= 4.x, the size of .reg2 section will be 400. Contents of .reg2 are { unsigned long vr[96]; unsigned long fcr; unsigned long fesr; unsigned long fid; unsigned long reserved; }; VR[96] means: (vr0~vr15) + (fr16~fr31), each Vector register is 128-bits, each Float register is 64 bits, the total size is (4*96). In addition, for fr0~fr15, each FRx is the lower 64 bits of the corresponding VRx. So fr0~fr15 and vr0~vr15 regisetrs use the same offset. --- gdb/csky-linux-tdep.c | 164 +++++++++++++++++++++++++++++++++++++----- gdb/csky-tdep.h | 3 + 2 files changed, 151 insertions(+), 16 deletions(-) diff --git a/gdb/csky-linux-tdep.c b/gdb/csky-linux-tdep.c index 440045e7713..08eb8f42768 100644 --- a/gdb/csky-linux-tdep.c +++ b/gdb/csky-linux-tdep.c @@ -36,6 +36,8 @@ #define SIZEOF_CSKY_GREGSET 34*4 /* Float regset fesr fsr fr0-fr31 for CK810. */ #define SIZEOF_CSKY_FREGSET 34*4 +/* Float regset vr0~vr15 fr15~fr31, reserved for CK810 when kernel 4.x. */ +#define SIZEOF_CSKY_FREGSET_K4X 400 /* Offset mapping table from core_section to regcache of general registers for ck810. */ @@ -118,15 +120,83 @@ csky_supply_fregset (const struct regset *regset, int fregset_num = ARRAY_SIZE (csky_fregset_offset); gdb_assert (len >= SIZEOF_CSKY_FREGSET); - for (i = 0; i < fregset_num; i++) + if (len == SIZEOF_CSKY_FREGSET) { - if ((regnum == csky_fregset_offset[i] || regnum == -1) - && csky_fregset_offset[i] != -1) - { - int num = csky_fregset_offset[i]; - offset += register_size (gdbarch, num); - regcache->raw_supply (csky_fregset_offset[i], fregs + offset); - } + for (i = 0; i < fregset_num; i++) + { + if ((regnum == csky_fregset_offset[i] || regnum == -1) + && csky_fregset_offset[i] != -1) + { + int num = csky_fregset_offset[i]; + offset += register_size (gdbarch, num); + regcache->raw_supply (csky_fregset_offset[i], fregs + offset); + } + } + } + else if (len == SIZEOF_CSKY_FREGSET_K4X) + { + /* When kernel version >= 4.x, .reg2 size will be 400. + Contents is { + unsigned long vr[96]; + unsigned long fcr; + unsigned long fesr; + unsigned long fid; + unsigned long reserved; + } + VR[96] means: (vr0~vr15) + (fr16~fr31), each Vector register is + 128-bits, each Float register is 64 bits, the total size is + (4*96). + + In addition, for fr0~fr15, each FRx is the lower 64 bits of the + corresponding VRx. So fr0~fr15 and vr0~vr15 regisetrs use the same + offset. */ + int fcr_regno[] = {122, 123, 121}; /* fcr, fesr, fid. */ + + /* Supply vr0~vr15. */ + for (i = 0; i < 16; i ++) + { + if (gdbarch_register_name (gdbarch, (CSKY_VR0_REGNUM + i))) + { + offset = 16 * i; + regcache->raw_supply (CSKY_VR0_REGNUM + i, + fregs + offset); + } + } + /* Supply fr0~fr15. */ + for (i = 0; i < 16; i ++) + { + if (gdbarch_register_name (gdbarch, (CSKY_FR0_REGNUM + i))) + { + offset = 16 * i; + regcache->raw_supply (CSKY_FR0_REGNUM + i, + fregs + offset); + } + } + /* Supply fr16~fr31. */ + for (i = 0; i < 16; i ++) + { + if (gdbarch_register_name (gdbarch, (CSKY_FR16_REGNUM + i))) + { + offset = (16 * 16) + (8 * i); + regcache->raw_supply (CSKY_FR16_REGNUM + i, + fregs + offset); + } + } + /* Supply fcr, fesr, fid. */ + for (i = 0; i < 3; i ++) + { + if (gdbarch_register_name (gdbarch, fcr_regno[i])) + { + offset = (16 * 16) + (16 * 8) + (4 * i); + regcache->raw_supply (fcr_regno[i], + fregs + offset); + } + } + } + else + { + warning (_("Unknow size %ld of section .reg2, can not get value" + " of float registers."), len); } } @@ -144,14 +214,73 @@ csky_collect_fregset (const struct regset *regset, int offset = 0; gdb_assert (len >= SIZEOF_CSKY_FREGSET); - for (regno = 0; regno < fregset_num; regno++) + if (len == SIZEOF_CSKY_FREGSET) + { + for (regno = 0; regno < fregset_num; regno++) + { + if ((regnum == csky_fregset_offset[regno] || regnum == -1) + && csky_fregset_offset[regno] != -1) + { + offset += register_size (gdbarch, csky_fregset_offset[regno]); + regcache->raw_collect (regno, fregs + offset); + } + } + } + else if (len == SIZEOF_CSKY_FREGSET_K4X) + { + /* When kernel version >= 4.x, .reg2 size will be 400. + Contents is { + unsigned long vr[96]; + unsigned long fcr; + unsigned long fesr; + unsigned long fid; + unsigned long reserved; + } + VR[96] means: (vr0~vr15) + (fr16~fr31), each Vector register is$ + 128-bits, each Float register is 64 bits, the total size is$ + (4*96).$ + + In addition, for fr0~fr15, each FRx is the lower 64 bits of the$ + corresponding VRx. So fr0~fr15 and vr0~vr15 regisetrs use the same$ + offset. */ + int i = 0; + int fcr_regno[] = {122, 123, 121}; /* fcr, fesr, fid. */ + + /* Supply vr0~vr15. */ + for (i = 0; i < 16; i ++) + { + if (gdbarch_register_name (gdbarch, (CSKY_VR0_REGNUM + i))) + { + offset = 16 * i; + regcache ->raw_collect (CSKY_VR0_REGNUM + i, + fregs + offset); + } + } + /* Supply fr16~fr31. */ + for (i = 0; i < 16; i ++) + { + if (gdbarch_register_name (gdbarch, (CSKY_FR16_REGNUM + i))) + { + offset = (16 * 16) + (8 * i); + regcache ->raw_collect (CSKY_FR16_REGNUM + i, + fregs + offset); + } + } + /* Supply fcr, fesr, fid. */ + for (i = 0; i < 3; i ++) + { + if (gdbarch_register_name (gdbarch, fcr_regno[i])) + { + offset = (16 * 16) + (16 * 8) + (4 * i); + regcache ->raw_collect (fcr_regno[i], + fregs + offset); + } + } + } + else { - if ((regnum == csky_fregset_offset[regno] || regnum == -1) - && csky_fregset_offset[regno] != -1) - { - offset += register_size (gdbarch, csky_fregset_offset[regno]); - regcache->raw_collect (regno, fregs + offset); - } + warning (_("Unknow size %ld of section .reg2, will not set value" + " of float registers."), len); } } @@ -166,7 +295,10 @@ static const struct regset csky_regset_float = { NULL, csky_supply_fregset, - csky_collect_fregset + csky_collect_fregset, + /* Allow .reg2 to have a different size, and the size of .reg2 should + always be bigger than SIZEOF_CSKY_FREGSET. */ + 1 }; /* Iterate over core file register note sections. */ diff --git a/gdb/csky-tdep.h b/gdb/csky-tdep.h index 4cfc0a5d086..3391a08c2e5 100644 --- a/gdb/csky-tdep.h +++ b/gdb/csky-tdep.h @@ -93,6 +93,9 @@ enum csky_regnum CSKY_PSR_REGNUM = CSKY_CR0_REGNUM, CSKY_MAX_REGISTER_SIZE = 16, + + /* Actually, the max regs number should be 1187. But if the + gdb stub does not send a tdesc-xml file to gdb, 253 works. */ CSKY_MAX_REGS = 253 }; -- 2.25.1