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[86.166.129.255]) by smtp.gmail.com with ESMTPSA id g5sm26493532wri.45.2021.11.10.01.40.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Nov 2021 01:40:48 -0800 (PST) Date: Wed, 10 Nov 2021 09:40:47 +0000 To: Vineet Gupta Subject: Re: [PATCH] sim: riscv: fix build breakage with rvv changes Message-ID: <20211110094047.GC2352@redhat.com> References: <20211029192856.3987778-1-vineetg@rivosinc.com> MIME-Version: 1.0 In-Reply-To: <20211029192856.3987778-1-vineetg@rivosinc.com> X-Operating-System: Linux/5.8.18-100.fc31.x86_64 (x86_64) X-Uptime: 09:30:28 up 4 days, 11:32, X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Andrew Burgess via Gdb-patches Reply-To: Andrew Burgess Cc: Dylan Reid , binutils@sourceware.org, Kito Cheng , gdb-patches@sourceware.org, Jim Wilson Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" * Vineet Gupta [2021-10-29 12:28:56 -0700]: > changes to gas for riscv vector extensions need to be propagated to sim > otherwise gdb fails to build on users/riscv/binutils-integration-branch > > This patch currently applies to that branch. > > Fixes: 144cceb058e "(RISC-V/rvv: Add rvv v0.10 instructions.)" > Reported-by: Dylan Reid > Signed-off-by: Vineet Gupta > --- > sim/riscv/ChangeLog-2021 | 4 ++++ > sim/riscv/sim-main.c | 3 ++- > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/sim/riscv/ChangeLog-2021 b/sim/riscv/ChangeLog-2021 > index e9aa74490f12..9ced6773bdd6 100644 > --- a/sim/riscv/ChangeLog-2021 > +++ b/sim/riscv/ChangeLog-2021 > @@ -1,3 +1,7 @@ > +2021-20-28 Vineet Gupta > + > + * sim-main.c (step_once): Fix match_func call per gas changes. > + > 2021-07-01 Mike Frysinger > > * configure: Regenerate. > diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c > index 0faf9395ae52..9b4f7c6c5aad 100644 > --- a/sim/riscv/sim-main.c > +++ b/sim/riscv/sim-main.c > @@ -956,6 +956,7 @@ void step_once (SIM_CPU *cpu) > sim_cia pc = cpu->pc; > const struct riscv_opcode *op; > int xlen = RISCV_XLEN (cpu); > + const char *error = NULL; Could this not be moved to the more inner scope? > > if (TRACE_ANY_P (cpu)) > trace_prefix (sd, cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu), > @@ -985,7 +986,7 @@ void step_once (SIM_CPU *cpu) > for (; op->name; op++) > { > /* Does the opcode match? */ > - if (! op->match_func (op, iw)) > + if (! op->match_func (op, iw, 0, /* check_constraints */ &error)) > continue; I've not looked at exactly what the purpose of error is here, does it just provide a reason why this function returns false? i.e. is it always OK for us to ignore it like this? Maybe a comment explaining briefly why we ignore something called error would be helpful. Maybe this email wasn't really intended for me, but you only need approval from the branch owner before merging to a user branch, and that certainly isn't me in this case, so I can't approve this patch for the branch. I've added Nelson and Jim to the CC list as, along with Kito, they wrote the original patch. And, as this patch doesn't currently apply to master, I can't approve this patch for master either. I assume this fix will be merged into the original patch (commit 144cceb058e59977f in the user branch) before the work is officially posted for inclusion in upstream master. Thanks, Andrew > /* Is this a pseudo-instruction and may we print it as such? */ > if (op->pinfo & INSN_ALIAS) > -- > 2.30.2 >