From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id QGuGLTtlXGEvHQAAWB0awg (envelope-from ) for ; Tue, 05 Oct 2021 10:46:19 -0400 Received: by simark.ca (Postfix, from userid 112) id B8A031EE1B; Tue, 5 Oct 2021 10:46:19 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,RDNS_DYNAMIC,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 1C4111EDDB for ; Tue, 5 Oct 2021 10:46:19 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B0E6F385AC2E for ; Tue, 5 Oct 2021 14:46:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B0E6F385AC2E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1633445178; bh=iilBjTN+uZYPT5PBGM7I0ghjgiyrI3fctuK7dOcHk9I=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=exchPtJGewSJWtDP56dCbEwB7lqpGCT1OIJhKb7ichbsMRg01AiOH2rh8DIvFlt6+ 0NMF8lg8C93bMEjMcRbTzVfcV5aZEK3ThU5wRE29gP4F2HVS0gDDGU3uWK2oshKOY1 f0/hSsUA4noiF706av8HN/YMk8pBE7XvOsUbM9EY= Received: from mail-qk1-x72d.google.com (mail-qk1-x72d.google.com [IPv6:2607:f8b0:4864:20::72d]) by sourceware.org (Postfix) with ESMTPS id D9FD7385840B for ; Tue, 5 Oct 2021 14:45:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D9FD7385840B Received: by mail-qk1-x72d.google.com with SMTP id q125so1027203qkd.12 for ; Tue, 05 Oct 2021 07:45:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iilBjTN+uZYPT5PBGM7I0ghjgiyrI3fctuK7dOcHk9I=; b=BCYikVk3nnv+40ybSTJyPA5JLvZYGcss4F3kz0dMBL4JQW0MqbUGFEtk0g+Uki5lvU YmHGOaCkiuTlGJaNumicQ4xYkeBG/z1pblAjIIpu1E4uH6ITA26IdEBbiByofzuulftx 5G8ZSV/J8ZIkkMq9N5L8aR6aG3YZBkDE5heEA7eqtwaEQwZP1Pfu0Ojdm+IR+o+yXDeh QIwZb10h9G2b/21e/9KPz2ci95QT8rLzwMDGU8oiK+UaO47JU1LV87k3yVRg1k1mv/BC CWXXdyDbZOL4KXGIvd8bfCS+sk0Qg5phNqrVTGgzroACphpXi/A1acIEEHcBPVvmyayW 22hw== X-Gm-Message-State: AOAM530pp81gJ5Pnv6ROn9/q46RUFL6lj/s0024q4LgwaE7AIqxkN4D6 iUCL7lXs2UUeIB9ZF0lwDnVXWkwEjpDZAw== X-Google-Smtp-Source: ABdhPJz8OJ2yIG8UbtbYvtVHLFBpgXQyWU6E6758g446weTRigwdQgb/R4c0qKXOGiOoyw9hKDnE5w== X-Received: by 2002:a37:986:: with SMTP id 128mr14854738qkj.487.1633445134460; Tue, 05 Oct 2021 07:45:34 -0700 (PDT) Received: from localhost.localdomain ([2804:7f0:4841:3c03:70c5:60d0:496d:7761]) by smtp.gmail.com with ESMTPSA id j7sm9445119qkl.125.2021.10.05.07.45.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Oct 2021 07:45:34 -0700 (PDT) To: gdb-patches@sourceware.org Subject: [PATCH 1/4] [ARM] Refactor some constants Date: Tue, 5 Oct 2021 11:45:18 -0300 Message-Id: <20211005144521.1965198-2-luis.machado@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211005144521.1965198-1-luis.machado@linaro.org> References: <20211005144521.1965198-1-luis.machado@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Luis Machado via Gdb-patches Reply-To: Luis Machado Cc: peter.maydell@linaro.org Errors-To: gdb-patches-bounces+public-inbox=simark.ca@sourceware.org Sender: "Gdb-patches" In preparation for the MVE extension patch, this one refactors some of the register-related constants we have for ARM. Basically I'm separating counting constants from numbering constants. For example, ARM_A1_REGNUM is a numbering constant, whereas ARM_NUM_ARG_REGS is a counting constant. --- gdb/arch/arm.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h index fa589fd0582..f6a155d6376 100644 --- a/gdb/arch/arm.h +++ b/gdb/arch/arm.h @@ -50,17 +50,23 @@ enum gdb_regnum { ARM_D31_REGNUM = ARM_D0_REGNUM + 31, ARM_FPSCR_REGNUM, - ARM_NUM_REGS, - /* Other useful registers. */ ARM_FP_REGNUM = 11, /* Frame register in ARM code, if used. */ THUMB_FP_REGNUM = 7, /* Frame register in Thumb code, if used. */ - ARM_NUM_ARG_REGS = 4, ARM_LAST_ARG_REGNUM = ARM_A4_REGNUM, - ARM_NUM_FP_ARG_REGS = 4, ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM }; +/* Register count constants. */ +enum arm_register_counts { + /* Number of argument registers. */ + ARM_NUM_ARG_REGS = 4, + /* Number of floating point argument registers. */ + ARM_NUM_FP_ARG_REGS = 4, + /* Number of registers (old, defined as ARM_FPSCR_REGNUM + 1. */ + ARM_NUM_REGS = ARM_FPSCR_REGNUM + 1 +}; + /* Enum describing the different kinds of breakpoints. */ enum arm_breakpoint_kinds { -- 2.25.1