From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id gCiKNknpq2CEYgAAWB0awg (envelope-from ) for ; Mon, 24 May 2021 13:58:33 -0400 Received: by simark.ca (Postfix, from userid 112) id DC8921F0FE; Mon, 24 May 2021 13:58:33 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 9EF461F11C for ; Mon, 24 May 2021 13:58:28 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 28BA33892452; Mon, 24 May 2021 17:58:28 +0000 (GMT) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2122.outbound.protection.outlook.com [40.107.223.122]) by sourceware.org (Postfix) with ESMTPS id 51D483858022 for ; Mon, 24 May 2021 17:58:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 51D483858022 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=wavecomp.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=fshahbazker@wavecomp.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mZG66c2AWvOucAhauSXbtJ5vwgAeblWEQHvJwk1SzspOwylkCOtIjOrvGN+dZRq17mH1eoay19aTzxnJ9RmzXWVOk86m2RQOEApbuI6Ma2ZioR4vN7wsZVGmkRzbFlCWOVQr75z6r8sMjD03YzCKhdyDbNA61DBJ1lENixSiYcUplL5hRUnKoTZNzVjMDULonC6bdWunGca7SF31X6rbT/7/DtTxQo+innj4lB+u/fwlmkVgjjM6QUCIzhjf44dS8tUQtzylSP4WNY/w61jQehN8hQxupz+zzuowRTpVqX9YbGk+o3kxXiZtFvAGmOCTTsxf2BfkSM2WC07mHOnrZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dOTAvZgSvG95eq+QJBUEW9s/VDkGHLmatfCMHdxMZtQ=; b=SW62D4Hu/fgTd2zgVNGZxvra4fQ//rzhchh7MKwvnrza5hdyDtdCQKp9i/lzZrDlMYfJrdQaTEykdIvd1TIRFRqfsFfkgfLxysqNp6I+btf8hHVMOa9WGkL2u3mkNfyWoBYwRkb4230LOOfrw6ftoFqYWF+SIwWbd2+TgOvPTLDtQWnUG5A9TrBYlsOsLkR8K/C+F77nQ/dtyTbSxdFcoH3A5ywEbK94aFp6JLsQpLpzp+P6YIU/11VKsHu7qkeQ4oO7DOKKHffgWXDyuqZoNppbHDmS2Ycaz3UrQBJyqECS0zlQR9qlmE+/m9ezL3ROfalOxrC6I4w/tSiQiN7BVg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wavecomp.com; dmarc=pass action=none header.from=wavecomp.com; dkim=pass header.d=wavecomp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=wavecomp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dOTAvZgSvG95eq+QJBUEW9s/VDkGHLmatfCMHdxMZtQ=; b=lRVi+Z9+lpOf02XMf0Qpj1cdTyy26THf7O6Gy92q3cbJGpr74p8y+uQUGuwlQ0LIl8jKJsSLJ1RWGzqT0LzaPhee0EvR6OdKX4VPtoPWIwm7O2fSzBe6MtaNtP31YwRarzx7s3KsS5kOr/Cac1MU7ynWu7jFvowO8OrtlOP518M= Authentication-Results: sourceware.org; dkim=none (message not signed) header.d=none;sourceware.org; dmarc=none action=none header.from=wavecomp.com; Received: from MW3PR22MB2299.namprd22.prod.outlook.com (2603:10b6:303:47::10) by MWHPR2201MB1343.namprd22.prod.outlook.com (2603:10b6:301:1c::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4150.26; Mon, 24 May 2021 17:58:22 +0000 Received: from MW3PR22MB2299.namprd22.prod.outlook.com ([fe80::e098:7822:150b:bb5b]) by MW3PR22MB2299.namprd22.prod.outlook.com ([fe80::e098:7822:150b:bb5b%7]) with mapi id 15.20.4150.027; Mon, 24 May 2021 17:58:22 +0000 From: Faraz Shahbazker To: gdb-patches@sourceware.org, Mike Frysinger Subject: [PATCH v2 3/5] sim: Add partial support for IEEE 754-2008 Date: Mon, 24 May 2021 23:28:00 +0530 Message-Id: <20210524175802.875687-4-fshahbazker@wavecomp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210524175802.875687-1-fshahbazker@wavecomp.com> References: <20210524175802.875687-1-fshahbazker@wavecomp.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable X-Originating-IP: [175.100.139.57] X-ClientProxiedBy: SJ0PR05CA0116.namprd05.prod.outlook.com (2603:10b6:a03:334::31) To MW3PR22MB2299.namprd22.prod.outlook.com (2603:10b6:303:47::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from frsxps.mipstec.com (175.100.139.57) by SJ0PR05CA0116.namprd05.prod.outlook.com (2603:10b6:a03:334::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4173.12 via Frontend Transport; Mon, 24 May 2021 17:58:20 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 77d3345e-35ab-40ce-0343-08d91edd84f5 X-MS-TrafficTypeDiagnostic: MWHPR2201MB1343: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vlbIX7gcekAcFR/CGFNhi5j5fNnXciNIa5ReTROHu79OQrmuKHzoVns7bkZdIglqYBZ3b7sKpU8abn1kBQutPC+epBHjZGZKrdq8HRZT5K+VizeYWVipA6nNNBvT4WRFaN7+24oWEu67B+ITWipe1HTMiSUjcUFyoZliwxx9Nq7onV46bfoQvXGA2btTvN+YyECsn0uvyAH9jq+aqqhc7ctQNSZdVmlO59lRtIftqi/O4oaKrBgbbsJ2PXhF0ynqcUR/dX8RMAOII11+t0Kre4Yo95pRtmW3Yk0GV69nnjw+/bPf5Xu5hiHGJUtQ7QHHpmxvMxKCAeQS2V54xQbr4/OTxpYPEQA8xhPre+XSCA2OnnrPRuHRQDu/yyRC9lrbJ41LJG9WB+ENH9dPRGpz9mmQ6a7xJgnhdmS6cLj30F9W3CcmvVztTM/YUI+1TnZhomtzIDx5d3gD5Tj0p7HEEF87SSTpneihLttS8LiUE4BxE21vam3ZfC4CwxJxpHDLaS1arwfYBKwOe9wXIrhCM06zymvh45WMFugxe3onRhEoxRABWbVb9y1bUwenvHM5Bh3n5ON1qH2rSJmhEl7HD3/8NXlcLDYLJjQDSDBt7cL/Bpvc9S53DuC+V1UbgH+Hjr1zSid9qj6jTTPNYMNa0w== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MW3PR22MB2299.namprd22.prod.outlook.com; PTR:; CAT:NONE; SFS:(366004)(396003)(39830400003)(136003)(346002)(376002)(478600001)(26005)(6666004)(107886003)(6512007)(4326008)(6506007)(16526019)(2906002)(6486002)(52116002)(38350700002)(6916009)(54906003)(316002)(956004)(8936002)(8676002)(86362001)(186003)(83380400001)(1076003)(66556008)(38100700002)(66946007)(66476007)(2616005)(5660300002)(36756003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?DwW+Lda1yI5UZF4EQRMn0q9ViUTPDVrW+TXMt1I25YSYFAK7WIs6fv8HPiLU?= =?us-ascii?Q?zwH019Y0caCqgAH7MDImp2fQHN0iEq06En9J3jgKovpqZl7Z+16Z6kO3C/hm?= =?us-ascii?Q?doFgzMV2aHzcBYAp6WHVuhXLFJr2QF/n7+8ptfGtRorSj+yHfq2GHF1yrk+S?= =?us-ascii?Q?9ZlyEaqptamIsRUnH4Nh4PUtax3OvCMoDlcwMeFfHsLVvhdkMhG8KTzDIHZH?= =?us-ascii?Q?tCHMZH2ptVNALvhi2e+4fBG14Jh48PjT+Aonmrzo1zqRtuDzjyz/huEO3qTd?= =?us-ascii?Q?NlXc6sbDj7HTrft5w2AOZ5kMTueKLN58Jge473ysbGuO6qFxIVaAAaBtUYeT?= =?us-ascii?Q?5MPPpVc5bX2MJ7Z+FitQ8odwKmtwm+krEGSQqvjh96lWBr+BRZym4+K2RD9l?= =?us-ascii?Q?SZDy07Y9Oi84mjfmEF4/+Yv7sC281cKDn3XpFoI7OWjKdngTGeUdlwBlgqab?= =?us-ascii?Q?F32tFC41MqBr2+fnAp6fm/zW3Cb1geRWz7wJAIb+Lr3TXk+eyPI0SkGL5TTO?= =?us-ascii?Q?Co+yl81CHlghTZ1NLQacCRW831K3Ud5hxlxo6MtrvvV3H+OLTM7Q1XGUpILw?= =?us-ascii?Q?aRkGcz+SDxmICg23FNHZI5RvJz/HrdKu0nyQzVxlFjG12kyOin+iQERq5Vn6?= =?us-ascii?Q?IucMVORr6KWW9J//mn2nOsCRPjsv72ByhIWIlhuss+CLrU13OB0O2r6rWgu6?= =?us-ascii?Q?6jlVsPFEWBqfWX3sHAf+Za2qE8HUdp9xkQQXUWZ6A3xaAmrEs+K23EOQ4dy+?= =?us-ascii?Q?TkV6IrUmhyu6UoJuHuesH5DPzlz8nNsgMJtKoiJHvUOzYvUzWWpCZ9UFH5QM?= =?us-ascii?Q?cxth0KkPLyXJVbGuBjAIedSWn2F8J8+xU7fL/MBf6m8RNzPYVEUNQJbdBlDz?= =?us-ascii?Q?BaFPGAds2v6kPMhGe+b42kb84FaWYhmDuRVMxQ5l+7ETZ8QVWx0EAVKYgS2b?= =?us-ascii?Q?iz3+SwHZKI0CxAiKCc4NXphOFNxKP6G3kZQsK3BHIIRFCMnvVBt1pigTol01?= =?us-ascii?Q?R/Ykgs6E05Yof1lzuUm9BE7VMViMIf+OuQjzPwsZiQQ3SALEglcOVXoYIt4v?= =?us-ascii?Q?7DZDJuf83Zs3SgZauACaNNGvMZmi+mpU8xkdPhFXmZGYM+S66By2sSIAxfxM?= =?us-ascii?Q?Zwrqnp6bNbjIhnue9zBy5ArAddDpqIUNGcrVWUdG7hQzI8N+thvhrKIPEaBr?= =?us-ascii?Q?QoAxfaMY+uTiUdDkcP5q4ysQxBmAgRvu4jXjxBiYKYIka55vanLxaRnSvGWB?= =?us-ascii?Q?0gUMuhmr0GEOHJTUgTtsikUK8z9G0yyfTHH5BZlZJqWB8mMjX68U+SkSzxQC?= =?us-ascii?Q?lO4E7DS0h5sdaMpbwu0Uco47?= X-OriginatorOrg: wavecomp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 77d3345e-35ab-40ce-0343-08d91edd84f5 X-MS-Exchange-CrossTenant-AuthSource: MW3PR22MB2299.namprd22.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2021 17:58:22.0206 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8WHjsphtpvN2k7t2sTbtnzGnd98/BWIIpeRK3TnyJlHNe6zawsd7mb4/kS+D3cStp01duEfw4ZWjhC4LJCULrAqj/M2iAyun0+SmkTtrr6g= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1343 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Faraz Shahbazker , Chao-ying Fu Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" 2021-05-24 Faraz Shahbazker sim/common/ChangeLog: * sim-fpu.c (sim_fpu_minmax_nan): New. (sim_fpu_max): Add variant behaviour for IEEE 754-2008. (sim_fpu_min): Likewise. (sim_fpu_is_un, sim_fpu_is_or): New. (sim_fpu_un, sim_fpu_or): New. (sim_fpu_current_mode): New. (sim_fpu_is_ieee754_2008, sim_fpu_is_ieee754_1985): New. (sim_fpu_set_mode): New. (sim_fpu_classify): New. * sim-fpu.h (sim_fpu_is_un, sim_fpu_is_or): New declarations. (sim_fpu_mode): New. (sim_fpu_is_ieee754_2008): New declaration. (sim_fpu_is_ieee754_1985): New declaration. (sim_fpu_set_mode): New declaration. (sim_fpu_classify): New declaration. --- Notes: Changes from v1: - whitespace and style fixes only sim/common/sim-fpu.c | 124 +++++++++++++++++++++++++++++++++++++++++-- sim/common/sim-fpu.h | 15 +++++- 2 files changed, 134 insertions(+), 5 deletions(-) diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c index 96b1776e986..26ada87c154 100644 --- a/sim/common/sim-fpu.c +++ b/sim/common/sim-fpu.c @@ -1005,6 +1005,29 @@ sim_fpu_op_nan (sim_fpu *f, const sim_fpu *l, const = sim_fpu *r) return 0; } =20 +/* NaN handling specific to min/max operations. */ + +INLINE_SIM_FPU (int) +sim_fpu_minmax_nan (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) +{ + if (sim_fpu_is_snan (l) + || sim_fpu_is_snan (r) + || sim_fpu_is_ieee754_1985 ()) + return sim_fpu_op_nan (f, l, r); + else + /* if sim_fpu_is_ieee754_2008() + && ((sim_fpu_is_qnan (l) || sim_fpu_is_qnan (r))) */ + { + /* In IEEE754-2008: + * "minNum/maxNum is ... the canonicalized number if one + * operand is a number and the other a quiet NaN." */ + if (sim_fpu_is_qnan (l)) + *f =3D *r; + else if (sim_fpu_is_qnan (r)) + *f =3D *l; + } +} + /* Arithmetic ops */ =20 INLINE_SIM_FPU (int) @@ -1553,7 +1576,7 @@ sim_fpu_max (sim_fpu *f, const sim_fpu *r) { if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) - return sim_fpu_op_nan (f, l, r); + return sim_fpu_minmax_nan (f, l, r); if (sim_fpu_is_infinity (l)) { if (sim_fpu_is_infinity (r) @@ -1616,7 +1639,7 @@ sim_fpu_min (sim_fpu *f, const sim_fpu *r) { if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) - return sim_fpu_op_nan (f, l, r); + return sim_fpu_minmax_nan (f, l, r); if (sim_fpu_is_infinity (l)) { if (sim_fpu_is_infinity (r) @@ -1677,7 +1700,7 @@ INLINE_SIM_FPU (int) sim_fpu_neg (sim_fpu *f, const sim_fpu *r) { - if (sim_fpu_is_snan (r)) + if (sim_fpu_is_ieee754_1985 () && sim_fpu_is_snan (r)) { *f =3D *r; f->class =3D sim_fpu_class_qnan; @@ -1700,7 +1723,7 @@ sim_fpu_abs (sim_fpu *f, { *f =3D *r; f->sign =3D 0; - if (sim_fpu_is_snan (r)) + if (sim_fpu_is_ieee754_1985 () && sim_fpu_is_snan (r)) { f->class =3D sim_fpu_class_qnan; return sim_fpu_status_invalid_snan; @@ -2255,6 +2278,23 @@ sim_fpu_is_gt (const sim_fpu *l, const sim_fpu *r) return is; } =20 +INLINE_SIM_FPU (int) +sim_fpu_is_un (const sim_fpu *l, + const sim_fpu *r) +{ + int is; + sim_fpu_un (&is, l, r); + return is; +} + +INLINE_SIM_FPU (int) +sim_fpu_is_or (const sim_fpu *l, + const sim_fpu *r) +{ + int is; + sim_fpu_or (&is, l, r); + return is; +} =20 /* Compare operators */ =20 @@ -2378,10 +2418,68 @@ sim_fpu_gt (int *is, return sim_fpu_lt (is, r, l); } =20 +INLINE_SIM_FPU (int) +sim_fpu_un (int *is, const sim_fpu *l, const sim_fpu *r) +{ + if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) + { + *is =3D 1; + return 0; + } + + *is =3D 0; + return 0; +} + +INLINE_SIM_FPU (int) +sim_fpu_or (int *is, const sim_fpu *l, const sim_fpu *r) +{ + sim_fpu_un (is, l, r); + + /* Invert result. */ + *is =3D !*is; + return 0; +} + +INLINE_SIM_FPU(int) +sim_fpu_classify (const sim_fpu *f) +{ + switch (f->class) + { + case sim_fpu_class_snan: return SIM_FPU_IS_SNAN; + case sim_fpu_class_qnan: return SIM_FPU_IS_QNAN; + case sim_fpu_class_infinity: + if (!f->sign) + return SIM_FPU_IS_PINF; + else + return SIM_FPU_IS_NINF; + case sim_fpu_class_zero: + if (!f->sign) + return SIM_FPU_IS_PZERO; + else + return SIM_FPU_IS_NZERO; + case sim_fpu_class_number: + if (!f->sign) + return SIM_FPU_IS_PNUMBER; + else + return SIM_FPU_IS_NNUMBER; + case sim_fpu_class_denorm: + if (!f->sign) + return SIM_FPU_IS_PDENORM; + else + return SIM_FPU_IS_NDENORM; + default: + fprintf (stderr, "Bad switch\n"); + abort (); + } + return 0; +} =20 /* A number of useful constants */ =20 #if EXTERN_SIM_FPU_P +static sim_fpu_mode sim_fpu_current_mode =3D sim_fpu_ieee754_1985; + const sim_fpu sim_fpu_zero =3D { sim_fpu_class_zero, 0, 0, 0 }; @@ -2410,6 +2508,24 @@ const sim_fpu sim_fpu_max64 =3D { bool sim_fpu_quiet_nan_inverted =3D false; #endif =20 +/* Specification swapping behaviour */ +INLINE_SIM_FPU (bool) +sim_fpu_is_ieee754_1985 (void) +{ + return (sim_fpu_current_mode =3D=3D sim_fpu_ieee754_1985); +} + +INLINE_SIM_FPU (bool) +sim_fpu_is_ieee754_2008 (void) +{ + return (sim_fpu_current_mode =3D=3D sim_fpu_ieee754_2008); +} + +INLINE_SIM_FPU (void) +sim_fpu_set_mode (const sim_fpu_mode m) +{ + sim_fpu_current_mode =3D m; +} =20 /* For debugging */ =20 diff --git a/sim/common/sim-fpu.h b/sim/common/sim-fpu.h index 51bb7d2be92..e4abe6ac96f 100644 --- a/sim/common/sim-fpu.h +++ b/sim/common/sim-fpu.h @@ -295,7 +295,8 @@ INLINE_SIM_FPU (double) sim_fpu_2d (const sim_fpu *d); /* INLINE_SIM_FPU (void) sim_fpu_f2 (sim_fpu *f, float s); */ INLINE_SIM_FPU (void) sim_fpu_d2 (sim_fpu *f, double d); =20 - +/* IEEE754-2008 classifiction function. */ +INLINE_SIM_FPU (int) sim_fpu_classify (const sim_fpu *f); =20 /* Specific number classes. =20 @@ -343,8 +344,20 @@ INLINE_SIM_FPU (int) sim_fpu_is_eq (const sim_fpu *l, = const sim_fpu *r); INLINE_SIM_FPU (int) sim_fpu_is_ne (const sim_fpu *l, const sim_fpu *r); INLINE_SIM_FPU (int) sim_fpu_is_ge (const sim_fpu *l, const sim_fpu *r); INLINE_SIM_FPU (int) sim_fpu_is_gt (const sim_fpu *l, const sim_fpu *r); +INLINE_SIM_FPU (int) sim_fpu_is_un (const sim_fpu *l, const sim_fpu *r); +INLINE_SIM_FPU (int) sim_fpu_is_or (const sim_fpu *l, const sim_fpu *r); =20 +/* Changes the behaviour of the library to IEEE754-2008 or IEEE754-1985. + * The default for the library is IEEE754-1985. */ +typedef enum +{ + sim_fpu_ieee754_1985, + sim_fpu_ieee754_2008, +} sim_fpu_mode; =20 +INLINE_SIM_FPU (bool) sim_fpu_is_ieee754_1985 (void); +INLINE_SIM_FPU (bool) sim_fpu_is_ieee754_2008 (void); +INLINE_SIM_FPU (void) sim_fpu_set_mode (const sim_fpu_mode m); =20 /* General number class and comparison operators. =20 --=20 2.25.1