From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id 2kiGAerAp2AGfQAAWB0awg (envelope-from ) for ; Fri, 21 May 2021 10:17:14 -0400 Received: by simark.ca (Postfix, from userid 112) id E482C1F11E; Fri, 21 May 2021 10:17:13 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=MAILING_LIST_MULTI, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id 7DD1C1E813 for ; Fri, 21 May 2021 10:17:12 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2A603398B865; Fri, 21 May 2021 14:17:11 +0000 (GMT) Received: from mail01.asahi-net.or.jp (mail01.asahi-net.or.jp [202.224.55.13]) by sourceware.org (Postfix) with ESMTP id D64253861936 for ; Fri, 21 May 2021 14:17:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org D64253861936 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=ysato@users.sourceforge.jp Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) (Authenticated sender: PQ4Y-STU) by mail01.asahi-net.or.jp (Postfix) with ESMTPA id 36D4B111F69; Fri, 21 May 2021 23:17:05 +0900 (JST) Received: from yo-satoh-debian.localdomain (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id 62ABD1C0463; Fri, 21 May 2021 23:17:05 +0900 (JST) From: Yoshinori Sato To: gdb-patches@sourceware.org Subject: [PATCH 1/2] sim: h8300 Fixed different behavior in preinc/predec. Date: Fri, 21 May 2021 23:16:54 +0900 Message-Id: <20210521141655.68398-1-ysato@users.sourceforge.jp> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" Fixed some addressing modes not working properly on the h8300. I have confirmed in the test case that the result is the same as the actual CPU. ChangeLog. 2021-05-21 Yoshinori Sato * sim-main.h (h8_typecodes): Add operand type OP_REG_DEC, OP_REG_INC. * compile.c (decode): Rewrite oprand type for specific case. (fetch_1): Add handling OP_REG_DEC and OP_REG_INC. (step_once): Fix operand fetch order. --- sim/h8300/compile.c | 52 ++++++++++++++++++++++++++++++++++++++++++-- sim/h8300/sim-main.h | 4 +++- 2 files changed, 53 insertions(+), 3 deletions(-) diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c index 365f8667c6a..885e347d3a6 100644 --- a/sim/h8300/compile.c +++ b/sim/h8300/compile.c @@ -1098,6 +1098,35 @@ decode (SIM_DESC sd, int addr, unsigned char *data, decoded_inst *dst) /* End of Processing for system calls. */ } + /* Use same register is specified for source + and destination. + the value of source will be the value after + address calculation. */ + if (OP_KIND(dst->opcode) != O_CMP && + OP_KIND(dst->src.type) == OP_REG && + (dst->src.reg & 7) == dst->dst.reg) { + switch (OP_KIND(dst->dst.type)) + { + case OP_POSTDEC: + dst->src.type = X(OP_REG_DEC, + OP_SIZE(dst->dst.type)); + break; + case OP_POSTINC: + dst->src.type = X(OP_REG_INC, + OP_SIZE(dst->dst.type)); + break; + case OP_PREINC: + if (OP_KIND(dst->opcode) == O_MOV) + dst->src.type = X(OP_REG_INC, + OP_SIZE(dst->dst.type)); + break; + case OP_PREDEC: + if (OP_KIND(dst->opcode) == O_MOV) + dst->src.type = X(OP_REG_DEC, + OP_SIZE(dst->dst.type)); + break; + } + } dst->next_pc = addr + len / 2; return; } @@ -1368,6 +1397,25 @@ fetch_1 (SIM_DESC sd, ea_type *arg, int *val, int twice) *val = abs; break; + case X (OP_REG_DEC, SB): /* Register direct, affected decrement byte. */ + *val = GET_B_REG (rn) - 1; + break; + case X (OP_REG_DEC, SW): /* Register direct, affected decrement word. */ + *val = GET_W_REG (rn) - 2; + break; + case X (OP_REG_DEC, SL): /* Register direct, affected decrement long. */ + *val = GET_L_REG (rn) - 4; + break; + case X (OP_REG_INC, SB): /* Register direct, affected increment byte. */ + *val = GET_B_REG (rn) + 1; + break; + case X (OP_REG_INC, SW): /* Register direct, affected increment word. */ + *val = GET_W_REG (rn) + 2; + break; + case X (OP_REG_INC, SL): /* Register direct, affected increment long. */ + *val = GET_L_REG (rn) + 4; + break; + case X (OP_MEM, SB): /* Why isn't this implemented? */ default: sim_engine_halt (sd, cpu, NULL, NULL_CIA, sim_stopped, SIM_SIGSEGV); @@ -1976,7 +2024,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case O (O_AND, SB): /* and.b */ /* Fetch rd and ea. */ - if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd)) + if (fetch2 (sd, &code->dst, &rd) || fetch (sd, &code->src, &ea)) goto end; res = rd & ea; goto log8; @@ -1997,7 +2045,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case O (O_OR, SB): /* or.b */ /* Fetch rd and ea. */ - if (fetch (sd, &code->src, &ea) || fetch2 (sd, &code->dst, &rd)) + if (fetch2 (sd, &code->dst, &rd) || fetch (sd, &code->src, &ea)) goto end; res = rd | ea; goto log8; diff --git a/sim/h8300/sim-main.h b/sim/h8300/sim-main.h index b6169b3bc12..686d5337639 100644 --- a/sim/h8300/sim-main.h +++ b/sim/h8300/sim-main.h @@ -83,7 +83,9 @@ enum h8_typecodes { /* FIXME: memory indirect? */ OP_INDEXB, /* Byte index mode */ OP_INDEXW, /* Word index mode */ - OP_INDEXL /* Long index mode */ + OP_INDEXL, /* Long index mode */ + OP_REG_DEC, /* Register direct. affect address decrement. */ + OP_REG_INC, /* Register direct. affect address increment. */ }; #include "sim-basics.h" -- 2.20.1