From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id QFW/MtYTpmCRUAAAWB0awg (envelope-from ) for ; Thu, 20 May 2021 03:46:30 -0400 Received: by simark.ca (Postfix, from userid 112) id C8C421EE14; Thu, 20 May 2021 03:46:30 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,RDNS_DYNAMIC, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id E0A901F11E for ; Thu, 20 May 2021 03:46:25 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 820D43951471; Thu, 20 May 2021 07:46:25 +0000 (GMT) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2125.outbound.protection.outlook.com [40.107.223.125]) by sourceware.org (Postfix) with ESMTPS id 575133950C76 for ; Thu, 20 May 2021 07:46:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 575133950C76 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=wavecomp.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=fshahbazker@wavecomp.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=R7/sNxlnYXreNOvfQB5fRpjXhujmM7gSB5+2ojyiCKEDqzHHWphdt6DnSPdtt8jB36158lVlj2xLLnGguVtxCBWrm7LZK03rKdnYiqwrGb6xfWx1v9D29j6hmpgW85y+CJyL3sTuPzeWw+lGxDgLIc5vKn5eexDu4sjJTeFlj6cbnuXytmy2fyUglZVuhlW/k3hebYpZYCurqEyv5CULZcSl2D9viyOJ6fTujpF9hJ3GiJqnMHAv/iLXEdCYqY99WE6JMEDJ4YxZEi/0YKCawOgRvpW4rcpDgh/zXBoqRZFNc1Wda0q/QrUFPV7YVIBiYJzI0gdNAq0ryDGrRc73qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CdU+Cc8MagAbpBpDGrcWY9XAwmul9fmVPMHCpRY1dxk=; b=Qa2wTxyK3p45V1IyPPA6rjZkAHgF4zjhoHEzNDXwuy39lU5WX8LecwB5WQ2LjyEys2sanDmu7l2nfk6mi/zASXhvxDr1jqAPTjKnHM1dHLUuNEILf2heSalWDos+MULBuItPvSeuFevdh1EqvTyao14GEbsIScB9KwAvptYHHXnckS6wphp58zM4FuRnl1lUEsg14Gi3kaGsUxguwfQcXC1Qmudkt6o2DxmTN6lM8wVpCrKvL8Ddjd0YUgjQhJl9DSBc0nEXtLC8goNP3MC4rzNLKS3wbrkQTIMHTyUtHrG5KNzzuAHVrKCeAiWJtEX8Yujb6qxx0YIBHi2KPAZWLg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wavecomp.com; dmarc=pass action=none header.from=wavecomp.com; dkim=pass header.d=wavecomp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=wavecomp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CdU+Cc8MagAbpBpDGrcWY9XAwmul9fmVPMHCpRY1dxk=; b=OKXuyXep5oAB9e3tvceHN1v5bp854Z5RXxwMQrH85RGiL/MmSpxpxyQyRKgD5w2GoDNHyjPiUHNnRpWXU4l3NirE82+x19+o1vsDzEu+Nr5QwEf3RilbzG+rOSYU2yRNYEP8i9CE3LR62v8T/kuULGyd9+7WKZ91iRjrPtz0khw= Authentication-Results: sourceware.org; dkim=none (message not signed) header.d=none;sourceware.org; dmarc=none action=none header.from=wavecomp.com; Received: from MW3PR22MB2299.namprd22.prod.outlook.com (2603:10b6:303:47::10) by MW2PR22MB2395.namprd22.prod.outlook.com (2603:10b6:302:b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.26; Thu, 20 May 2021 07:46:18 +0000 Received: from MW3PR22MB2299.namprd22.prod.outlook.com ([fe80::e098:7822:150b:bb5b]) by MW3PR22MB2299.namprd22.prod.outlook.com ([fe80::e098:7822:150b:bb5b%6]) with mapi id 15.20.4129.034; Thu, 20 May 2021 07:46:18 +0000 From: Faraz Shahbazker To: gdb-patches@sourceware.org, Mike Frysinger Subject: [PATCH 3/5] sim: Add partial support for IEEE 754-2008 Date: Thu, 20 May 2021 13:15:52 +0530 Message-Id: <20210520074554.1465327-4-fshahbazker@wavecomp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210520074554.1465327-1-fshahbazker@wavecomp.com> References: <20210520074554.1465327-1-fshahbazker@wavecomp.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable X-Originating-IP: [123.201.194.96] X-ClientProxiedBy: PN2PR01CA0088.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:23::33) To MW3PR22MB2299.namprd22.prod.outlook.com (2603:10b6:303:47::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (123.201.194.96) by PN2PR01CA0088.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:23::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.25 via Frontend Transport; Thu, 20 May 2021 07:46:15 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5adf1e72-0a52-4252-67d1-08d91b6359fd X-MS-TrafficTypeDiagnostic: MW2PR22MB2395: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QhW3kO86X+fgLUEDCWg+2e5t5Dt4+omdQpvuPPqimvB1LOlx5lFaBtRVbRy+C6j/God5sRfBHHzTvYNiVSnWST9pc6s8s/Ywf1l55z9AH31VSlXvUgcXIQ0gba4vUdbQ0l+IjYYtFoH//BfWtisbyXu0m+fxjJfJkI/ULkDmCCvUDMZEYYKipCUqKCo9g7Vnz5PIAO+n7DFXoTMQWCGtQa0QhbElwVdfYkEwgbBYvu5+SppayiDQuIw7uFU02BmljDisxFhI5q9lQXtIMTv+toV5Lgm6Sihj3G4VSJ1tN76cJQ5H/NFB8Fa8z7Z/trZXcYpqZzmvlpbrkJGiHNLxIGFUgFV9sU19QoTcor+uAAKkeBYT9Xm3vJnjTRH1SV7ffA3Zk8P6pDBQel1kzSqIR/7M23a6xnqSWkiLwhNsubAhImJrISg3ZDrx+qfM0CM58iQlztAkpJuCsGFFiF/xSCm57S546QFB4m01Rt2Q+azLsGl6Q75M0yIkX96kn9IFV2FnMpP0gf9ihC89yq+ljLmJEQ2/2Z+7Hb00foMpsyDR12PHni6PzMJTcFHaqF24Kp6RRwMNunCu9r6yA1MiqOhB4EtUqFERyG/dOhu4C/gLMzoBGdCzEtPqIDRzgYxulGiSr+2juDObOaXVRxz9FQ== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MW3PR22MB2299.namprd22.prod.outlook.com; PTR:; CAT:NONE; SFS:(346002)(39840400004)(136003)(396003)(366004)(376002)(6666004)(38350700002)(38100700002)(6506007)(26005)(8676002)(186003)(66946007)(52116002)(16526019)(66556008)(86362001)(66476007)(1076003)(54906003)(2906002)(8936002)(316002)(956004)(2616005)(6512007)(6916009)(478600001)(6486002)(83380400001)(4326008)(107886003)(5660300002)(36756003); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?3M65Kgyrz9OEPJviOfRVEX2wZNyrvmEcGVAcilfIfhx/5nwRBofnS0FEuRL0?= =?us-ascii?Q?f/audKHvyHIYpoyfjiPaEH6UTND45Bd/aEnVhA391gsa1BxwS/nibPlhEZzy?= =?us-ascii?Q?DjPPJPbfNe9LjpW6ywJdnJNexukR+FtBGJAvfDys3EfrqqbAj5WTvMvVTJnB?= =?us-ascii?Q?PQ+o6HCTtLCk3Q98m0hS5M4sw8l0U3BHjz2yMLk8/SUXLC7z9gsaWdW1CSE5?= =?us-ascii?Q?BAK+Z51wbKqH/7NX5Ixhn/BPJpdi0/gY8vQ6mxo+uWOU2visEG6YHL879oMV?= =?us-ascii?Q?ZWSL3Tdlh6UE6wN/+3zaHn8kWY3a0jvQkBcBYGcXjljN8mLgfY6RKsXNdH8c?= =?us-ascii?Q?mVkv+AY/8mTpHoMRWM+NuHhvgLuG1HFUhP5DJwO8P6JGfT3QmzP/A988AMcL?= =?us-ascii?Q?azEgH76H+15Y4AOegkiduhFm98I6hHCRfThX88RiTmGtnzmuvk4bSnExHAYP?= =?us-ascii?Q?WsDJP5EX8LgfGiqZ1yrmKSl3efGwhg8sfpPZe9kRx5ZOYSsYU3VAZeNafdtO?= =?us-ascii?Q?HxnbsxFri//XEJ19e/y8Q/yL2Mh3WimxeaM7VaoLjUc0r9PdXVSkE9rSjxCE?= =?us-ascii?Q?6ZKP3QQCwHrhNkjzPMrRP6EplF27nU/v5bFZTsPD45I9heIG+ifqWQz7zh5Z?= =?us-ascii?Q?q4TTemI4umSSb85W+coZAPwcC+9IFWoYb6MkEjD+GPX0IW9PKNUboSudljKX?= =?us-ascii?Q?zwhbgLI73UdWqTNXFVGQfTjB3cX/2+VQ3+Wq+dD+dcIz4wq+8ncGEAdWXC2v?= =?us-ascii?Q?eQY59huAaCCGQNkKAKCV/+nP8duIjlyw/eLEoMOZWm5B8DLG37K1m1JL6NdE?= =?us-ascii?Q?VBJVikjgo0aKNgURCvYIzU7ynqyn1XRV6MYi++k4up7n56E24SsbrplQfkAF?= =?us-ascii?Q?fIm1m7c2BhBArHU4NhHKbKIaOUjjtaHnuh9PToVvhyzfQ5MnibGg0jzdjw/+?= =?us-ascii?Q?vQj7hUvyoYQvJrsJAOtQmQk5sBp/x6RTUeCX6aSgmdHgYvymJy0AfoCqhC8M?= =?us-ascii?Q?qLLKKUcfnXNtH2XyY+nErXbSoe6o5Bw/QxJAEuvieQ+NVpsf6i5e0jxOmTwD?= =?us-ascii?Q?ZEOgT5iATTFfaQeeQdMBTB9xOZnCpd1HJVO1ioO0NHM1Oay4TF3wvNYPNfIt?= =?us-ascii?Q?9dipkUIjO0I2F8fZjqwF+KzulTv7fDY/8PVoptTjwL22sADY5XrSG9JEzwRL?= =?us-ascii?Q?ct57LVsUaD8/P7w9dTwe8aOppejIRI9VoCZmgYvgLLTEb5oMe97CCKHl4wAG?= =?us-ascii?Q?uqh+SU9vIzPq60qbnn8LsMg8ZKZpqva2KITgpoVNo9bK7+eNZMX45IDOFFZ7?= =?us-ascii?Q?1lhWLdhXB1MoYxiP6AYfCNh1?= X-OriginatorOrg: wavecomp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5adf1e72-0a52-4252-67d1-08d91b6359fd X-MS-Exchange-CrossTenant-AuthSource: MW3PR22MB2299.namprd22.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2021 07:46:17.9020 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 00njZCyi/bOa2QL4nmqJrUiaqEn9aLDc+OBZcXo2Tnwmu66djFLt52QNEfq4sVrOiyIa2tNgzLeQSYc3FnB4RiIFz+cyty7Sn7RYExxuWmw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR22MB2395 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chao-ying Fu , Faraz Shahbazker , "Maciej W . Rozycki" Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" 2021-05-19 Faraz Shahbazker sim/common/ChangeLog: * sim-fpu.c (sim_fpu_minmax_nan): New. (sim_fpu_max): Add variant behaviour for IEEE 754-2008. (sim_fpu_min): Likewise. (sim_fpu_is_un, sim_fpu_is_or): New. (sim_fpu_un, sim_fpu_or): New. (sim_fpu_current_mode, sim_fpu_set_mode): New. (sim_fpu_is_ieee754_2008, sim_fpu_is_ieee754_1985): New. (sim_fpu_classify): New. * sim-fpu.h (sim_fpu_is_un, sim_fpu_is_or): New declarations. (sim_fpu_current_mode, sim_fpu_set_mode): New. (sim_fpu_is_ieee754_2008): New declaration. (sim_fpu_is_ieee754_1985): New declaration. (sim_fpu_classify): New declaration. --- sim/common/sim-fpu.c | 126 +++++++++++++++++++++++++++++++++++++++++-- sim/common/sim-fpu.h | 15 +++++- 2 files changed, 137 insertions(+), 4 deletions(-) diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c index 7a2f5c4a605..1cc12d6d831 100644 --- a/sim/common/sim-fpu.c +++ b/sim/common/sim-fpu.c @@ -1005,6 +1005,29 @@ sim_fpu_op_nan (sim_fpu *f, const sim_fpu *l, const = sim_fpu *r) return 0; } =20 +/* NaN handling specific to min/max operations. */ + +INLINE_SIM_FPU (int) +sim_fpu_minmax_nan (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) +{ + if (sim_fpu_is_snan (l) + || sim_fpu_is_snan (r) + || sim_fpu_is_ieee754_1985 ()) + return sim_fpu_op_nan (f, l, r); + else + /* if sim_fpu_is_ieee754_2008() + && ((sim_fpu_is_qnan (l) || sim_fpu_is_qnan (r))) */ + { + /* In IEEE754-2008: + * "minNum/maxNum is ... the canonicalized number if one + * operand is a number and the other a quiet NaN." */ + if (sim_fpu_is_qnan (l)) + *f =3D *r; + else if (sim_fpu_is_qnan (r)) + *f =3D *l; + } +} + /* Arithmetic ops */ =20 INLINE_SIM_FPU (int) @@ -1553,7 +1576,7 @@ sim_fpu_max (sim_fpu *f, const sim_fpu *r) { if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) - return sim_fpu_op_nan (f, l, r); + return sim_fpu_minmax_nan (f, l, r); if (sim_fpu_is_infinity (l)) { if (sim_fpu_is_infinity (r) @@ -1616,7 +1639,7 @@ sim_fpu_min (sim_fpu *f, const sim_fpu *r) { if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) - return sim_fpu_op_nan (f, l, r); + return sim_fpu_minmax_nan (f, l, r); if (sim_fpu_is_infinity (l)) { if (sim_fpu_is_infinity (r) @@ -1700,7 +1723,7 @@ sim_fpu_abs (sim_fpu *f, { *f =3D *r; f->sign =3D 0; - if (sim_fpu_is_snan (r)) + if (sim_fpu_is_ieee754_1985 () && sim_fpu_is_snan (r)) { f->class =3D sim_fpu_class_qnan; return sim_fpu_status_invalid_snan; @@ -2255,6 +2278,23 @@ sim_fpu_is_gt (const sim_fpu *l, const sim_fpu *r) return is; } =20 +INLINE_SIM_FPU (int) +sim_fpu_is_un (const sim_fpu *l, + const sim_fpu *r) +{ + int is; + sim_fpu_un (&is, l, r); + return is; +} + +INLINE_SIM_FPU (int) +sim_fpu_is_or (const sim_fpu *l, + const sim_fpu *r) +{ + int is; + sim_fpu_or (&is, l, r); + return is; +} =20 /* Compare operators */ =20 @@ -2378,10 +2418,72 @@ sim_fpu_gt (int *is, return sim_fpu_lt (is, r, l); } =20 +INLINE_SIM_FPU (int) +sim_fpu_un (int *is, + const sim_fpu *l, + const sim_fpu *r) +{ + if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) + { + *is =3D 1; + return 0; + } + + *is =3D 0; + return 0; +} + +INLINE_SIM_FPU (int) +sim_fpu_or (int *is, + const sim_fpu *l, + const sim_fpu *r) +{ + sim_fpu_un (is, l, r); + + /* Invert result */ + *is =3D (*is) ? 0 : 1; + return 0; +} + +INLINE_SIM_FPU(int) +sim_fpu_classify(const sim_fpu *f) +{ + switch (f->class) + { + case sim_fpu_class_snan: return SIM_FPU_IS_SNAN; + case sim_fpu_class_qnan: return SIM_FPU_IS_QNAN; + case sim_fpu_class_infinity: + if (!f->sign) + return SIM_FPU_IS_PINF; + else + return SIM_FPU_IS_NINF; + case sim_fpu_class_zero: + if (!f->sign) + return SIM_FPU_IS_PZERO; + else + return SIM_FPU_IS_NZERO; + case sim_fpu_class_number: + if (!f->sign) + return SIM_FPU_IS_PNUMBER; + else + return SIM_FPU_IS_NNUMBER; + case sim_fpu_class_denorm: + if (!f->sign) + return SIM_FPU_IS_PDENORM; + else + return SIM_FPU_IS_NDENORM; + default: + fprintf (stderr, "Bad switch\n"); + abort (); + } + return 0; +} =20 /* A number of useful constants */ =20 #if EXTERN_SIM_FPU_P +static sim_fpu_mode sim_fpu_current_mode =3D sim_fpu_ieee754_1985; + const sim_fpu sim_fpu_zero =3D { sim_fpu_class_zero, 0, 0, 0 }; @@ -2410,6 +2512,24 @@ const sim_fpu sim_fpu_max64 =3D { int sim_fpu_quiet_nan_inverted =3D 0; #endif =20 +/* Specification swapping behaviour */ +INLINE_SIM_FPU (int) +sim_fpu_is_ieee754_1985 (void) +{ + return (sim_fpu_current_mode =3D=3D sim_fpu_ieee754_1985); +} + +INLINE_SIM_FPU (int) +sim_fpu_is_ieee754_2008 (void) +{ + return (sim_fpu_current_mode =3D=3D sim_fpu_ieee754_2008); +} + +INLINE_SIM_FPU (void) +sim_fpu_set_mode (const sim_fpu_mode m) +{ + sim_fpu_current_mode =3D m; +} =20 /* For debugging */ =20 diff --git a/sim/common/sim-fpu.h b/sim/common/sim-fpu.h index 1eb5cae6c08..511338aa923 100644 --- a/sim/common/sim-fpu.h +++ b/sim/common/sim-fpu.h @@ -295,7 +295,8 @@ INLINE_SIM_FPU (double) sim_fpu_2d (const sim_fpu *d); /* INLINE_SIM_FPU (void) sim_fpu_f2 (sim_fpu *f, float s); */ INLINE_SIM_FPU (void) sim_fpu_d2 (sim_fpu *f, double d); =20 - +/* IEEE754-2008 classifiction function. */ +INLINE_SIM_FPU (int) sim_fpu_classify (const sim_fpu *f); =20 /* Specific number classes. =20 @@ -343,8 +344,20 @@ INLINE_SIM_FPU (int) sim_fpu_is_eq (const sim_fpu *l, = const sim_fpu *r); INLINE_SIM_FPU (int) sim_fpu_is_ne (const sim_fpu *l, const sim_fpu *r); INLINE_SIM_FPU (int) sim_fpu_is_ge (const sim_fpu *l, const sim_fpu *r); INLINE_SIM_FPU (int) sim_fpu_is_gt (const sim_fpu *l, const sim_fpu *r); +INLINE_SIM_FPU (int) sim_fpu_is_un (const sim_fpu *l, const sim_fpu *r); +INLINE_SIM_FPU (int) sim_fpu_is_or (const sim_fpu *l, const sim_fpu *r); =20 +/* Changes the behaviour of the library to IEEE754-2008 or IEEE754-1985. + * The default for the library is IEEE754-1985. */ +typedef enum +{ + sim_fpu_ieee754_1985, + sim_fpu_ieee754_2008, +} sim_fpu_mode; =20 +INLINE_SIM_FPU (int) sim_fpu_is_ieee754_1985 (void); +INLINE_SIM_FPU (int) sim_fpu_is_ieee754_2008 (void); +INLINE_SIM_FPU (void) sim_fpu_set_mode (const sim_fpu_mode m); =20 /* General number class and comparison operators. =20 --=20 2.25.1