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Rozycki" Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" 2021-05-19 Faraz Shahbazker sim/common/ChangeLog: * sim-fpu.c (sim_fpu_op_nan): New. (sim_fpu_add): Factor out NaN operand handling with a call to sim_fpu_op_nan. (sim_fpu_sub, sim_fpu_mul, sim_fpu_div): Likewise. (sim_fpu_rem, sim_fpu_max, sim_fpu_min): Likewise. --- sim/common/sim-fpu.c | 189 +++++++------------------------------------ 1 file changed, 31 insertions(+), 158 deletions(-) diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c index b5e96b9a324..7a2f5c4a605 100644 --- a/sim/common/sim-fpu.c +++ b/sim/common/sim-fpu.c @@ -986,7 +986,24 @@ sim_fpu_round_64 (sim_fpu *f, return do_round (f, 1, round, denorm); } =20 +/* NaN handling for binary operations. */ =20 +INLINE_SIM_FPU (int) +sim_fpu_op_nan (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) +{ + if (sim_fpu_is_snan (l) || sim_fpu_is_snan (r)) + { + *f =3D sim_fpu_is_snan (l) ? *l : *r; + f->class =3D sim_fpu_class_qnan; + return sim_fpu_status_invalid_snan; + } + ASSERT (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)); + if (sim_fpu_is_qnan (l)) + *f =3D *l; + else /* if (sim_fpu_is_qnan (r)) */ + *f =3D *r; + return 0; +} =20 /* Arithmetic ops */ =20 @@ -995,28 +1012,8 @@ sim_fpu_add (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) { - if (sim_fpu_is_snan (l)) - { - *f =3D *l; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_snan (r)) - { - *f =3D *r; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_qnan (l)) - { - *f =3D *l; - return 0; - } - if (sim_fpu_is_qnan (r)) - { - *f =3D *r; - return 0; - } + if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) + return sim_fpu_op_nan (f, l, r);x if (sim_fpu_is_infinity (l)) { if (sim_fpu_is_infinity (r) @@ -1144,28 +1141,8 @@ sim_fpu_sub (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) { - if (sim_fpu_is_snan (l)) - { - *f =3D *l; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_snan (r)) - { - *f =3D *r; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_qnan (l)) - { - *f =3D *l; - return 0; - } - if (sim_fpu_is_qnan (r)) - { - *f =3D *r; - return 0; - } + if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) + return sim_fpu_op_nan (f, l, r); if (sim_fpu_is_infinity (l)) { if (sim_fpu_is_infinity (r) @@ -1298,28 +1275,8 @@ sim_fpu_mul (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) { - if (sim_fpu_is_snan (l)) - { - *f =3D *l; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_snan (r)) - { - *f =3D *r; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_qnan (l)) - { - *f =3D *l; - return 0; - } - if (sim_fpu_is_qnan (r)) - { - *f =3D *r; - return 0; - } + if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) + return sim_fpu_op_nan (f, l, r); if (sim_fpu_is_infinity (l)) { if (sim_fpu_is_zero (r)) @@ -1423,30 +1380,8 @@ sim_fpu_div (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) { - if (sim_fpu_is_snan (l)) - { - *f =3D *l; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_snan (r)) - { - *f =3D *r; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_qnan (l)) - { - *f =3D *l; - f->class =3D sim_fpu_class_qnan; - return 0; - } - if (sim_fpu_is_qnan (r)) - { - *f =3D *r; - f->class =3D sim_fpu_class_qnan; - return 0; - } + if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) + return sim_fpu_op_nan (f, l, r); if (sim_fpu_is_infinity (l)) { if (sim_fpu_is_infinity (r)) @@ -1556,30 +1491,8 @@ sim_fpu_rem (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) { - if (sim_fpu_is_snan (l)) - { - *f =3D *l; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_snan (r)) - { - *f =3D *r; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_qnan (l)) - { - *f =3D *l; - f->class =3D sim_fpu_class_qnan; - return 0; - } - if (sim_fpu_is_qnan (r)) - { - *f =3D *r; - f->class =3D sim_fpu_class_qnan; - return 0; - } + if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) + return sim_fpu_op_nan (f, l, r); if (sim_fpu_is_infinity (l)) { *f =3D sim_fpu_qnan; @@ -1639,28 +1552,8 @@ sim_fpu_max (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) { - if (sim_fpu_is_snan (l)) - { - *f =3D *l; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_snan (r)) - { - *f =3D *r; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_qnan (l)) - { - *f =3D *l; - return 0; - } - if (sim_fpu_is_qnan (r)) - { - *f =3D *r; - return 0; - } + if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) + return sim_fpu_op_nan (f, l, r); if (sim_fpu_is_infinity (l)) { if (sim_fpu_is_infinity (r) @@ -1722,28 +1615,8 @@ sim_fpu_min (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) { - if (sim_fpu_is_snan (l)) - { - *f =3D *l; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_snan (r)) - { - *f =3D *r; - f->class =3D sim_fpu_class_qnan; - return sim_fpu_status_invalid_snan; - } - if (sim_fpu_is_qnan (l)) - { - *f =3D *l; - return 0; - } - if (sim_fpu_is_qnan (r)) - { - *f =3D *r; - return 0; - } + if (sim_fpu_is_nan (l) || sim_fpu_is_nan (r)) + return sim_fpu_op_nan (f, l, r); if (sim_fpu_is_infinity (l)) { if (sim_fpu_is_infinity (r) --=20 2.25.1