From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id 1crIOdATpmCRUAAAWB0awg (envelope-from ) for ; Thu, 20 May 2021 03:46:24 -0400 Received: by simark.ca (Postfix, from userid 112) id BFA0A1EE14; Thu, 20 May 2021 03:46:24 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id A1AD81EE14 for ; Thu, 20 May 2021 03:46:22 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 614203950C81; Thu, 20 May 2021 07:46:22 +0000 (GMT) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2137.outbound.protection.outlook.com [40.107.94.137]) by sourceware.org (Postfix) with ESMTPS id 516AE3848024 for ; Thu, 20 May 2021 07:46:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 516AE3848024 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=wavecomp.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=fshahbazker@wavecomp.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TCVn5SKVMFBMOkuwtVFFAqlvIXt4ZuUS5m/dW81KU2iQInzQ1/m5qTiKCtj2UJIJPogwXO4ovJrah54wPITeydgruwiot3BW8XChNd3rwpGjDijwdhvRd7ks6sAwQXK/gSN1dZvtyfUjcwvf6nl3M0b0TMhN1dX+l+mZrjFZcESirtHFyfo0Ie0cVB01lpIiE47OXPEOsCSSmDnpZFWOH8/sdWyAroSofQ9GofAjiXp3Z1D5QK9ZCdmcQJBfUV5MmMXo/sdYQJ6N38ZrkmrhSlEFcX1AX/KjWZCPSK8zXqHhO9/13/BSH+a4CUoHCDTQxh/RxX7U63lIBvGk/GsgLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0dplecGx7F6YFs7+ssbrDrmBbXFqt5Xqc4Op1SihRH8=; b=P2XODBTFtZRkvTBQRoRsnki9azb3ivcr/zxXZQ3NNzSN4akSjRYRJiVZhgXnIMt7Dqr1iKzGMgzGIf889Ykeq9Y9VOmyjT+xTEXGMO7I8N6bpnG0PR6rY932t7VFfRP6LjRFHmZ4WlQCGUoxMGh1LcbMxC9fcehAT/Wl3yAH/IoGXklK4dzQ2OGtipHLh4ThXVfIU2whZg1p8/XXXM0l1R+jhHQyptcgw/RffuKXyCcxpYUvhQKelPJRHxtAS0dz9UJijMGgt+o17BMHMpBxjOvNdVTa4ZxJZWg7REC6VPfdB8ESitAYTEKaKomEP7enD0N5+fet9BuCYYylquWcMQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=wavecomp.com; dmarc=pass action=none header.from=wavecomp.com; dkim=pass header.d=wavecomp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=wavecomp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0dplecGx7F6YFs7+ssbrDrmBbXFqt5Xqc4Op1SihRH8=; b=KrCBIot7j9KyvC9vBITTuSdECeCqWztgQzSqUWtxx4u4fGnS0JeJpSNhLnRur596/sDysnJwxVUuoHmBgqmpN6OjQ1ioLBV/nBG9c3X5mxtrOnAw4cDrAjZYw5cHdUEfyn/qqiqKFAbUg1mbYou4xBE0pcWO2PbsRTlG4q7CE80= Authentication-Results: sourceware.org; dkim=none (message not signed) header.d=none;sourceware.org; dmarc=none action=none header.from=wavecomp.com; Received: from MW3PR22MB2299.namprd22.prod.outlook.com (2603:10b6:303:47::10) by MWHPR2201MB1344.namprd22.prod.outlook.com (2603:10b6:301:25::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.28; Thu, 20 May 2021 07:46:12 +0000 Received: from MW3PR22MB2299.namprd22.prod.outlook.com ([fe80::e098:7822:150b:bb5b]) by MW3PR22MB2299.namprd22.prod.outlook.com ([fe80::e098:7822:150b:bb5b%6]) with mapi id 15.20.4129.034; Thu, 20 May 2021 07:46:12 +0000 From: Faraz Shahbazker To: gdb-patches@sourceware.org, Mike Frysinger Subject: [PATCH 1/5] sim: Allow toggling of quiet NaN-bit semantics Date: Thu, 20 May 2021 13:15:50 +0530 Message-Id: <20210520074554.1465327-2-fshahbazker@wavecomp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210520074554.1465327-1-fshahbazker@wavecomp.com> References: <20210520074554.1465327-1-fshahbazker@wavecomp.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable X-Originating-IP: [123.201.194.96] X-ClientProxiedBy: PN2PR01CA0088.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:23::33) To MW3PR22MB2299.namprd22.prod.outlook.com (2603:10b6:303:47::10) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (123.201.194.96) by PN2PR01CA0088.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:23::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4129.25 via Frontend Transport; Thu, 20 May 2021 07:46:10 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f3c27cec-9cd7-427e-ecfe-08d91b6356d0 X-MS-TrafficTypeDiagnostic: MWHPR2201MB1344: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bdetOcJfujv+RQ2HFqhs7MZU4ybrBPF0XvNhRrpeamoaWp6daSdEVqWjkP7TeOPJhF3sNS3VdP16E9m9VlxaQz0ue2/nmQiaCWtxKo11HOwixmVXczHsTzNK7Brp5Str+aOisQzlxxnQhT7qpoiL76APaLJA8ciOeO245QBFDAXgqLfmcINMoUONW64dcb9IgO4ChMKgPNdA0S2tiAGaLXCFKN2+OZWFpY3iCr6l+FvWo5Dl3xSU3FbXwtqI0gq46uPFy3qMDr9Cy+bsWLgr66RlYbu/h6xhmIk4COTYVIu3q4nUOo6i+Gptr1JSd+c5aMXzlpcM1QW6pniVPa5uEi4FpnGE3S2CKbKzNM72eQM6Z3rpk8nh1Rt8yLDNMaZ1gGpDrLwkOGjTVVGnMgSkRk0GWaxi7Lnb5GuMJuefflVHvZePVUxe5ufCLQs06kgf/azutUry4unPyOwrAwBsPeKRH0tgLnujxjNeCTiOlKfT8aG7Si89pC/StvSZbiDF9BYbhUnFZg/PnZUGsFdO2Rv4S59AjAzlbC1SD5l/4aSO35t+VifHSismcYupIUGnEARXMLUZio8HoS1E/0jSzq63/vjDyY2XOTzz6ZKFzwXmcy1ZE4xfXx7uO0t4yGtFiCXJAgvVfY+S0B47IY8BclmJ666PQ1s8xMl4JaiStFP/mrJXEGIbsrt0WgtkQVw9YM6HqIajyhbE/kExOOvbjJ3XS38Z6xdEGf0q1m2EvzsNVuMiQmtrQi/NHutRCYDVxpJRwqIj3Rlqe1F/4DW3Hg== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MW3PR22MB2299.namprd22.prod.outlook.com; PTR:; CAT:NONE; SFS:(346002)(376002)(366004)(39830400003)(136003)(396003)(8936002)(107886003)(2906002)(26005)(8676002)(6512007)(36756003)(38100700002)(1076003)(38350700002)(16526019)(186003)(66946007)(6666004)(478600001)(54906003)(316002)(6506007)(83380400001)(6916009)(66476007)(66556008)(6486002)(956004)(4326008)(2616005)(5660300002)(86362001)(52116002); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?Yi115krGE0gvog9Pao1rA/fB/pJC1+yg1cU+Eg+Qie66RVeXYSaUSW37sK9o?= =?us-ascii?Q?uOeQZdP+d9v6FKMrMBRLgs79rnqXmh/nlb94i7uHbtSKuQSN6cY21X82ulNI?= =?us-ascii?Q?Eg29ugeSOeHoXTShegslzMNk1B5ZYkophpNJ2eqY7c5NMd5AMlU5K8uhYHZO?= =?us-ascii?Q?xx9JnC2+g+DZEYyWo2QRIDbwO8wZ7zW+83Vo61iVzI9HQZ0Na9wqmLgP51WK?= =?us-ascii?Q?0feX674YkN+VPp8g/PmBLmip2eiUMeYVFbhfqQoFRHoJg6e462pVB9yt3AW8?= =?us-ascii?Q?/GryuJMbgc+dB3+IfvI6oLiCkkqMQHaaWqUEgQvVbUpgEfPwsIl90/38YSLu?= =?us-ascii?Q?tGQaGZ7AroV0rORXbtiRLUwW11SqUnzBR+u7E3Pe5oKhMt/g4+GsywldYaXL?= =?us-ascii?Q?9rrPtmYQC9NaAql8uHy7VJVDfQNNwQgCA7j3sU6zKQbto6KUkff+xf1RxTXV?= =?us-ascii?Q?sB9htSEiPp3NQYesGscaeRVh5MH/aC5bdQMo9QPSApWLrI42wpTeXEPHoQJ6?= =?us-ascii?Q?VzHEVzlvNsY5+U5kbZUMi5IkY3UErhmfExIATFvoC/JlJMt1fYIqiSZyfVEc?= =?us-ascii?Q?5eA5SFBGJjUXMBGRfB8R3XnJY2IX/iILtO8Ir0n/dYrBIWSbt7xClN+6ZMX+?= =?us-ascii?Q?EReWMKoEOf/NxygIqiNR/YT8So8R6ML0TdFUy7r7mm//scp/a2vNwi737q3c?= =?us-ascii?Q?I0Xbur2FjE9/4yad2AXjbZzM7AZierESkIXiVtvqIHh8zYDuglMGMHcGaGK1?= =?us-ascii?Q?C0ab2ZmCFUOAOKEXn20eIg+n2dOzMNM9ADsR0gr82X8jllYEhDh/A8kNw1TD?= =?us-ascii?Q?+EOjxMx5oVNAXSqAMvR2NUXo6Wsa9hw4fMvV6xRxyHOSOJ9blJJrehe2ahlb?= =?us-ascii?Q?XVwMv/xeyRF0a0qZRL72mgPtS7SLoK6DkI7SqYzBLl5OukWu6j68a+X2tNCl?= =?us-ascii?Q?BLO2qi6lQ0b7nUw4By8xV7xrI+vo5j6FqyuqCNN1rnR93CN+N7YVwcAHc9wV?= =?us-ascii?Q?b90bWFQI5lM7qZjY6TT6lkUFzFhnpFJDP0Yc/JQxsriy5AhEza3IN1ZlIHnS?= =?us-ascii?Q?bypfjv1CLMGgGKzvfgk6FiTU1KzPXah4H6n2tIBjOka9qq9zF2G58qtKmNbx?= =?us-ascii?Q?5T7TJ3gAfjgxZsRdLAknFQOnHsJIHB/GsUDntlLXojLlmvgBCPAsoGlvnEmZ?= =?us-ascii?Q?mdneIf8z1m1Rvgl7tlC6OQNLkI3e+yZxEKnE56+/tCqx4/25ndYGMdSdrB2x?= =?us-ascii?Q?a1izioYKE/Yzve+ce93DyHDadz1xWN87g+BEt8Ie8Jlh5Ta+9InqBJmi0JcR?= =?us-ascii?Q?zA8fSdCyGx7ytgaYft/TACqE?= X-OriginatorOrg: wavecomp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f3c27cec-9cd7-427e-ecfe-08d91b6356d0 X-MS-Exchange-CrossTenant-AuthSource: MW3PR22MB2299.namprd22.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2021 07:46:12.5455 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BxIVvFFopRXnnvDxWHjJhoHpPT/sJNsz+dNF0OGEM01H3Tkyn8PxNHWFNpb268LlKmfTO/qlnoV/nbBhtTnkCHQbbVqIn5La5XYiijby03o= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1344 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chao-ying Fu , Faraz Shahbazker , "Maciej W . Rozycki" Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" IEEE754-1985 specifies the top bit of the mantissa as an indicator of signalling vs. quiet NaN, but does not define the precise semantics. Most architectures treat this bit as indicating quiet NaN, but legacy (pre-R6) MIPS goes the other way and treats it as signalling NaN. This used to be controlled by a macro that was only defined for MIPS. This patch replaces the macro with a variable to track the current semantics of the NaN bit and allows differentiation between older (pre-R6) and and newer MIPS cores. 2021-05-19 Faraz Shahbazker sim/common/ChangeLog: * sim-fpu.c (sim_fpu_quiet_nan_inverted): New. (pack_fpu, unpack_fpu): Allow reversal of quiet NaN semantics. * sim-fpu.h (sim_fpu_quiet_nan_inverted): New extern. sim/mips/ChangeLog: * cp1.h (fcsr_NAN2008_mask, fcsr_NAN2008_shift): New. * mips.igen (check_fpu): Select default quiet NaN mode for legacy MIPS. * sim-main.h (SIM_QUIET_NAN_NEGATED): Remove. --- sim/common/sim-fpu.c | 35 ++++++++++++++++++++--------------- sim/common/sim-fpu.h | 2 ++ sim/mips/cp1.h | 4 ++++ sim/mips/mips.igen | 3 +++ sim/mips/sim-main.h | 3 --- 5 files changed, 29 insertions(+), 18 deletions(-) diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c index fe8ecf8a3ce..b5e96b9a324 100644 --- a/sim/common/sim-fpu.c +++ b/sim/common/sim-fpu.c @@ -198,11 +198,10 @@ pack_fpu (const sim_fpu *src, /* Force fraction to correct class. */ fraction =3D src->fraction; fraction >>=3D NR_GUARDS; -#ifdef SIM_QUIET_NAN_NEGATED - fraction |=3D QUIET_NAN - 1; -#else - fraction |=3D QUIET_NAN; -#endif + if (sim_fpu_quiet_nan_inverted) + fraction |=3D QUIET_NAN - 1; + else + fraction |=3D QUIET_NAN; break; case sim_fpu_class_snan: sign =3D src->sign; @@ -210,11 +209,10 @@ pack_fpu (const sim_fpu *src, /* Force fraction to correct class. */ fraction =3D src->fraction; fraction >>=3D NR_GUARDS; -#ifdef SIM_QUIET_NAN_NEGATED - fraction |=3D QUIET_NAN; -#else - fraction &=3D ~QUIET_NAN; -#endif + if (sim_fpu_quiet_nan_inverted) + fraction |=3D QUIET_NAN; + else + fraction &=3D ~QUIET_NAN; break; case sim_fpu_class_infinity: sign =3D src->sign; @@ -372,11 +370,10 @@ unpack_fpu (sim_fpu *dst, unsigned64 packed, int is_d= ouble) /* Non zero fraction, means NaN. */ dst->sign =3D sign; dst->fraction =3D (fraction << NR_GUARDS); -#ifdef SIM_QUIET_NAN_NEGATED - qnan =3D (fraction & QUIET_NAN) =3D=3D 0; -#else - qnan =3D fraction >=3D QUIET_NAN; -#endif + if (sim_fpu_quiet_nan_inverted) + qnan =3D (fraction & QUIET_NAN) =3D=3D 0; + else + qnan =3D fraction >=3D QUIET_NAN; if (qnan) dst->class =3D sim_fpu_class_qnan; else @@ -2530,6 +2527,14 @@ const sim_fpu sim_fpu_max32 =3D { const sim_fpu sim_fpu_max64 =3D { sim_fpu_class_number, 0, LSMASK64 (NR_FRAC_GUARD, NR_GUARDS64), NORMAL_E= XPMAX64 }; + +/* IEEE 754-1985 specifies the top bit of the mantissa as an indicator + of signalling vs. quiet NaN, but does not specify the semantics. + Most architectures treat this bit as quiet NaN, but legacy (pre-R6) + MIPS goes the other way and treats it as signalling. This variable + tracks the current semantics of the NaN bit and allows differentiation + between pre-R6 and R6 MIPS cores. */ +int sim_fpu_quiet_nan_inverted =3D 0; #endif =20 =20 diff --git a/sim/common/sim-fpu.h b/sim/common/sim-fpu.h index 89e6de7e35f..1eb5cae6c08 100644 --- a/sim/common/sim-fpu.h +++ b/sim/common/sim-fpu.h @@ -375,7 +375,9 @@ enum { INLINE_SIM_FPU (int) sim_fpu_is (const sim_fpu *l); INLINE_SIM_FPU (int) sim_fpu_cmp (const sim_fpu *l, const sim_fpu *r); =20 +/* Toggle quiet NaN semantics. */ =20 +extern int sim_fpu_quiet_nan_inverted; =20 /* A number of useful constants. */ =20 diff --git a/sim/mips/cp1.h b/sim/mips/cp1.h index 3a78bf4c6b3..0babdc28eca 100644 --- a/sim/mips/cp1.h +++ b/sim/mips/cp1.h @@ -40,6 +40,10 @@ along with this program. If not, see . */ #define fcsr_RM_mask (0x00000003) #define fcsr_RM_shift (0) =20 +/* FCSR bits for IEEE754-2008 compliance. */ +#define fcsr_NAN2008_mask (0x00040000) +#define fcsr_NAN2008_shift (18) + #define fenr_FS (0x00000004) =20 /* Macros to update and retrieve the FCSR condition-code bits. This diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 522cad6fe45..8240a859bfd 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -5050,6 +5050,9 @@ { if (! COP_Usable (1)) SignalExceptionCoProcessorUnusable (1); + + FCSR &=3D ~fcsr_NAN2008_mask; + sim_fpu_quiet_nan_inverted =3D 1; } =20 =20 diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 8c9abfa0b0b..e8531405ebc 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -20,9 +20,6 @@ along with this program. If not, see . */ #ifndef SIM_MAIN_H #define SIM_MAIN_H =20 -/* MIPS uses an unusual format for floating point quiet NaNs. */ -#define SIM_QUIET_NAN_NEGATED - #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER= ), (ERROR)) =20 --=20 2.25.1