From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id sCkzJR0ie2CaOgAAWB0awg (envelope-from ) for ; Sat, 17 Apr 2021 13:59:57 -0400 Received: by simark.ca (Postfix, from userid 112) id 967421F104; Sat, 17 Apr 2021 13:59:57 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id B62D61EE0E for ; Sat, 17 Apr 2021 13:59:55 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A01843896C2B; Sat, 17 Apr 2021 17:59:54 +0000 (GMT) Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by sourceware.org (Postfix) with ESMTPS id 7FEBA389853F for ; Sat, 17 Apr 2021 17:59:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 7FEBA389853F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=jimw@sifive.com Received: by mail-pj1-x102b.google.com with SMTP id nm3-20020a17090b19c3b029014e1bbf6c60so12083449pjb.4 for ; Sat, 17 Apr 2021 10:59:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/YXSRS9i+VfTF15gL7D1TVOxUZtiDYqyCr9omkJpbac=; b=I4SGj3mxNEa2vcUVD0EAibEnsy0uFy24EflZoGLJSFh8zAjSsE2ezGF1yxufNsM+8r K1XH3tn4s0xWHNIkoXTr0uXYA4VpBOC0gDjHPfr+66Axrcg6IsjxOPONBBF8XgWsnPsD 0iaj6RttZVZNYZnnDrwHGOoWqNUIR3r1fK+an8FppRMvlSeMqiqE8U9BD5rhV/3Zkafi 3sxoEO0lHo5mhUNmhLLoZia7o/iCNRi9zFJy7R+SsfSVHkjlUr4Ki19tFjcTfyrVuLzI h/WSeJRVBTx+nxqIokVCbqAOE5yz23A5Z7DLZzZQZ+lfVj0HevGeaPrY2sNGdwObHEQy um3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/YXSRS9i+VfTF15gL7D1TVOxUZtiDYqyCr9omkJpbac=; b=f4BC5wLI3nQ42JM69jYfHseQYjvs7lCdpUmC0QI3PZBGIhCq44S7j6LhdICbgxXuaf yLdeuuJjbLtupzA4vWgYGstlym4J67xQbYJ00hkMBcZzn5czguMzxSwWmEMX/mb2wzRe 65uaZ62HZJhFIE/78NsIr3/V54JPxiAaTuWiivvmTX6wkrM2VhD3fNcqHuzXYeU7ftmh IYyQRJbrhcN7AUYoNGMnNvba1FOA8MBRgIGo8Ha0IGsSV2P1lihBCE0rhS3hS89S7ov3 XvmTgbjVuJfnZet1VuJwYM1KEmEq/3y4Sx7IqwHAFbkc3e0C5ZKC/h6BNrMGLC/Sy3ZP IdJw== X-Gm-Message-State: AOAM532F4QoWtRQ8YMlrUtNzZ3nooRUbYytq/iEHon7Lv2YreqwMqMUZ aCmr6bFb/7Z4Ax/bUZhjIqw4gKUC80ebng== X-Google-Smtp-Source: ABdhPJwYfRNuMxY5b/BYBae3cGnjzbaHekdSdip4oYEwc++miWu40PXu2LQ2jyNfGaaK/8yE2ubYug== X-Received: by 2002:a17:902:6b05:b029:e9:2810:7e59 with SMTP id o5-20020a1709026b05b02900e928107e59mr15382780plk.76.1618682372385; Sat, 17 Apr 2021 10:59:32 -0700 (PDT) Received: from rohan.hsd1.ca.comcast.net ([2601:646:c180:b150:1820:3ed4:975:3fbe]) by smtp.gmail.com with ESMTPSA id u4sm5030705pfk.56.2021.04.17.10.59.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Apr 2021 10:59:32 -0700 (PDT) From: Jim Wilson To: gdb-patches@sourceware.org Subject: [PATCH 24/24] RISC-V sim: Fix divw and remw. Date: Sat, 17 Apr 2021 10:58:31 -0700 Message-Id: <20210417175831.16413-25-jimw@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210417175831.16413-1-jimw@sifive.com> References: <20210417175831.16413-1-jimw@sifive.com> X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" From: Kito Cheng According to spec, result is -2^31 only when divisor is -1 AND dividend is -2^31 for divw. According to spec, result is 0 only when divisor is -1 AND dividend is -2^31 for remw. sim/riscv/ * sim-main.c (execute_m): New local dividend32_max. Set it. Use in cases MATCH_DIVW and MATCH_REMW. --- sim/riscv/sim-main.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 3974f61..d92f756 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -2020,9 +2020,11 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) const char *rs1_name = riscv_gpr_names_abi[rs1]; const char *rs2_name = riscv_gpr_names_abi[rs2]; unsigned_word tmp, dividend_max; + signed_word dividend32_max; sim_cia pc = cpu->pc + 4; dividend_max = -((unsigned_word) 1 << (WITH_TARGET_WORD_BITSIZE - 1)); + dividend32_max = INT32_MIN; switch (op->match) { @@ -2041,7 +2043,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) TRACE_INSN (cpu, "divw %s, %s, %s; // %s = %s / %s", rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name); RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name); - if (EXTEND32 (cpu->regs[rs2]) == -1) + if (EXTEND32 (cpu->regs[rs1]) == dividend32_max + && EXTEND32 (cpu->regs[rs2]) == -1) tmp = 1 << 31; else if (EXTEND32 (cpu->regs[rs2])) tmp = EXTEND32 (cpu->regs[rs1]) / EXTEND32 (cpu->regs[rs2]); @@ -2122,7 +2125,8 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) TRACE_INSN (cpu, "remw %s, %s, %s; // %s = %s %% %s", rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name); RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name); - if (EXTEND32 (cpu->regs[rs2]) == -1) + if (EXTEND32 (cpu->regs[rs1]) == dividend32_max + && EXTEND32 (cpu->regs[rs2]) == -1) tmp = 0; else if (EXTEND32 (cpu->regs[rs2])) tmp = EXTEND32 (cpu->regs[rs1]) % EXTEND32 (cpu->regs[rs2]); -- 2.7.4