From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id iCZBBlbLEWA2TwAAWB0awg (envelope-from ) for ; Wed, 27 Jan 2021 15:21:42 -0500 Received: by simark.ca (Postfix, from userid 112) id 1428A1EF82; Wed, 27 Jan 2021 15:21:41 -0500 (EST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,RDNS_NONE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from sourceware.org (unknown [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id A4DB71EF7A for ; Wed, 27 Jan 2021 15:21:40 -0500 (EST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DF88C398B841; Wed, 27 Jan 2021 20:21:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DF88C398B841 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1611778898; bh=hccl9fqcZrbBQCRHTMRq2/cBRspZIPPo/SSVY45fuig=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=rTNHxCwkFfh5+1Uf7aMGk1alenDn952KgpxwLRMKypPoE+/QZtxtoORz25pTv+/vQ 4BbJ5RQxUGxPsx0SILdnaD73GY9ff9Mmk+OHVO3RnOxKpcPjFzEHgo8ogv1kzY4Fgs 2qco8lgAB1PZD1IrTX6/+opF6vv9cm2njiIARA78= Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by sourceware.org (Postfix) with ESMTPS id 01C75398B826 for ; Wed, 27 Jan 2021 20:21:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 01C75398B826 Received: by mail-qt1-x82e.google.com with SMTP id w20so230505qta.0 for ; Wed, 27 Jan 2021 12:21:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hccl9fqcZrbBQCRHTMRq2/cBRspZIPPo/SSVY45fuig=; b=Ftv7jtXG8bELh9HWC851uaipZy//GDiwHqT2oNGP3Ajlob4EpM4dC0KU8veRnF8j2T OxBNoHDJb+9+zFSUdsDLhqkTRdRVqwKFPJWaHJXLtw5Q7VJ6FH3ZNe4O+F82doGwvCQd kJs5nEch1idJaCoUjvRK8o/ZrkHzBdkirlh0p/b948HUGUR/GLl9ndBgoM+mpJ9XXPYW q7z5JQjxH8/l734N0jf55h3q3uwmA3JoSnOahNjxHCvEzyXq/UhwHj3kNoxoUXzlEJmN KtnD2HEbGDw04SHe2QI8UQHOg6NoSAWuh53KCnCzZe5UwAQ27fmqIeNz1DP3Utx8pW4I NPug== X-Gm-Message-State: AOAM533QQAdxdxeQbX+gM7ibVRdm/WmFuULUDIWu9lL30bdsXPYGqBzC LBXyOr4sNjBgjviXqQoB+J/C6OAw0zNxsg== X-Google-Smtp-Source: ABdhPJy9IQ8iiyKa2520l2mdowh/El+wAGfo34oU5NCI5w+JgwgY3CZags/9unAnkw8gRZjazgW6+Q== X-Received: by 2002:ac8:4990:: with SMTP id f16mr11162345qtq.184.1611778895387; Wed, 27 Jan 2021 12:21:35 -0800 (PST) Received: from localhost.localdomain ([2804:7f0:8284:874d:b82c:87fc:4324:adab]) by smtp.gmail.com with ESMTPSA id b194sm1854531qkc.102.2021.01.27.12.21.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Jan 2021 12:21:35 -0800 (PST) To: gdb-patches@sourceware.org Subject: [PATCH v5 10/25] AArch64: Add MTE register set support for GDB and gdbserver Date: Wed, 27 Jan 2021 17:20:57 -0300 Message-Id: <20210127202112.2485702-11-luis.machado@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210127202112.2485702-1-luis.machado@linaro.org> References: <20210127202112.2485702-1-luis.machado@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Luis Machado via Gdb-patches Reply-To: Luis Machado Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" Updates on v4: - Use get_ptrace_pid in a couple spots. -- AArch64 MTE support in the Linux kernel exposes a new register through ptrace. This patch adds the required code to support it. include/ChangeLog: YYYY-MM-DD Luis Machado * elf/common.h (NT_ARM_TAGGED_ADDR_CTRL): Define. gdb/ChangeLog: YYYY-MM-DD Luis Machado * aarch64-linux-nat.c (fetch_mteregs_from_thread): New function. (store_mteregs_to_thread): New function. (aarch64_linux_nat_target::fetch_registers): Update to call fetch_mteregs_from_thread. (aarch64_linux_nat_target::store_registers): Update to call store_mteregs_to_thread. * aarch64-tdep.c (aarch64_mte_register_names): New struct. (aarch64_cannot_store_register): Handle MTE registers. (aarch64_gdbarch_init): Initialize and setup MTE registers. * aarch64-tdep.h (gdbarch_tdep) : New field. : New method. * arch/aarch64-linux.h (AARCH64_LINUX_SIZEOF_MTE): Define. gdbserver/ChangeLog: YYYY-MM-DD Luis Machado * linux-aarch64-low.cc (aarch64_fill_mteregset): New function. (aarch64_store_mteregset): New function. (aarch64_regsets): Add MTE register set entry. (aarch64_sve_regsets): Add MTE register set entry. --- gdb/aarch64-linux-nat.c | 68 ++++++++++++++++++++++++++++++++++ gdb/aarch64-tdep.c | 24 ++++++++++++ gdb/aarch64-tdep.h | 9 +++++ gdb/arch/aarch64-mte-linux.h | 3 ++ gdbserver/linux-aarch64-low.cc | 29 +++++++++++++++ include/elf/common.h | 3 ++ 6 files changed, 136 insertions(+) diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c index c56880e33d..fe3ba44c55 100644 --- a/gdb/aarch64-linux-nat.c +++ b/gdb/aarch64-linux-nat.c @@ -461,6 +461,58 @@ fetch_pauth_masks_from_thread (struct regcache *regcache) &pauth_regset[1]); } +/* Fill GDB's register array with the MTE register values from + the current thread. */ + +static void +fetch_mteregs_from_thread (struct regcache *regcache) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + int regno = tdep->mte_reg_base; + + gdb_assert (regno != -1); + + uint64_t tag_ctl = 0; + struct iovec iovec; + + iovec.iov_base = &tag_ctl; + iovec.iov_len = sizeof (tag_ctl); + + int tid = get_ptrace_pid (regcache->ptid ()); + if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0) + perror_with_name (_("unable to fetch MTE registers.")); + + regcache->raw_supply (regno, &tag_ctl); +} + +/* Store to the current thread the valid MTE register set in the GDB's + register array. */ + +static void +store_mteregs_to_thread (struct regcache *regcache) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + int regno = tdep->mte_reg_base; + + gdb_assert (regno != -1); + + uint64_t tag_ctl = 0; + + if (REG_VALID != regcache->get_register_status (regno)) + return; + + regcache->raw_collect (regno, (char *) &tag_ctl); + + struct iovec iovec; + + iovec.iov_base = &tag_ctl; + iovec.iov_len = sizeof (tag_ctl); + + int tid = get_ptrace_pid (regcache->ptid ()); + if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0) + perror_with_name (_("unable to store MTE registers.")); +} + /* Implement the "fetch_registers" target_ops method. */ void @@ -479,6 +531,9 @@ aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, if (tdep->has_pauth ()) fetch_pauth_masks_from_thread (regcache); + + if (tdep->has_mte ()) + fetch_mteregs_from_thread (regcache); } else if (regno < AARCH64_V0_REGNUM) fetch_gregs_from_thread (regcache); @@ -493,6 +548,11 @@ aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)) fetch_pauth_masks_from_thread (regcache); } + + /* Fetch individual MTE registers. */ + if (tdep->has_mte () + && (regno == tdep->mte_reg_base)) + fetch_mteregs_from_thread (regcache); } /* Implement the "store_registers" target_ops method. */ @@ -510,6 +570,9 @@ aarch64_linux_nat_target::store_registers (struct regcache *regcache, store_sveregs_to_thread (regcache); else store_fpregs_to_thread (regcache); + + if (tdep->has_mte ()) + store_mteregs_to_thread (regcache); } else if (regno < AARCH64_V0_REGNUM) store_gregs_to_thread (regcache); @@ -517,6 +580,11 @@ aarch64_linux_nat_target::store_registers (struct regcache *regcache, store_sveregs_to_thread (regcache); else store_fpregs_to_thread (regcache); + + /* Store MTE registers. */ + if (tdep->has_mte () + && (regno == tdep->mte_reg_base)) + store_mteregs_to_thread (regcache); } /* Fill register REGNO (if it is a general-purpose register) in diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 685c50b84d..44833eb94d 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -172,6 +172,12 @@ static const char *const aarch64_pauth_register_names[] = "pauth_cmask" }; +static const char *const aarch64_mte_register_names[] = +{ + /* Tag Control Register. */ + "tag_ctl" +}; + /* AArch64 prologue cache structure. */ struct aarch64_prologue_cache { @@ -3346,6 +3352,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) bool valid_p = true; int i, num_regs = 0, num_pseudo_regs = 0; int first_pauth_regnum = -1, pauth_ra_state_offset = -1; + int first_mte_regnum = -1; /* Use the vector length passed via the target info. Here -1 is used for no SVE, and 0 is unset. If unset then use the vector length from the existing @@ -3383,6 +3390,8 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu"); feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve"); feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth"); + const struct tdesc_feature *feature_mte + = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.mte"); if (feature_core == nullptr) return nullptr; @@ -3453,6 +3462,20 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */ } + /* Add the MTE registers. */ + if (feature_mte != NULL) + { + first_mte_regnum = num_regs; + /* Validate the descriptor provides the mandatory MTE registers and + allocate their numbers. */ + for (i = 0; i < ARRAY_SIZE (aarch64_mte_register_names); i++) + valid_p &= tdesc_numbered_register (feature_mte, tdesc_data.get (), + first_mte_regnum + i, + aarch64_mte_register_names[i]); + + num_regs += i; + } + if (!valid_p) return nullptr; @@ -3470,6 +3493,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->pauth_reg_base = first_pauth_regnum; tdep->pauth_ra_state_regnum = (feature_pauth == NULL) ? -1 : pauth_ra_state_offset + num_regs; + tdep->mte_reg_base = first_mte_regnum; set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call); set_gdbarch_frame_align (gdbarch, aarch64_frame_align); diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h index f6d24292f8..7bf612b012 100644 --- a/gdb/aarch64-tdep.h +++ b/gdb/aarch64-tdep.h @@ -100,6 +100,15 @@ struct gdbarch_tdep { return pauth_reg_base != -1; } + + /* First MTE register. This is -1 if no MTE registers are available. */ + int mte_reg_base; + + /* Returns true if the target supports MTE. */ + bool has_mte () const + { + return mte_reg_base != -1; + } }; const target_desc *aarch64_read_description (uint64_t vq, bool pauth_p, diff --git a/gdb/arch/aarch64-mte-linux.h b/gdb/arch/aarch64-mte-linux.h index c6a91c2db4..4124e80543 100644 --- a/gdb/arch/aarch64-mte-linux.h +++ b/gdb/arch/aarch64-mte-linux.h @@ -25,4 +25,7 @@ #define HWCAP2_MTE (1 << 18) #endif +/* The MTE regset consists of a single 64-bit register. */ +#define AARCH64_LINUX_SIZEOF_MTE 8 + #endif /* ARCH_AARCH64_LINUX_H */ diff --git a/gdbserver/linux-aarch64-low.cc b/gdbserver/linux-aarch64-low.cc index 14493c1fbe..a066d963a5 100644 --- a/gdbserver/linux-aarch64-low.cc +++ b/gdbserver/linux-aarch64-low.cc @@ -261,6 +261,29 @@ aarch64_store_pauthregset (struct regcache *regcache, const void *buf) &pauth_regset[1]); } +/* Fill BUF with the MTE registers from the regcache. */ + +static void +aarch64_fill_mteregset (struct regcache *regcache, void *buf) +{ + uint64_t *mte_regset = (uint64_t *) buf; + int mte_base = find_regno (regcache->tdesc, "tag_ctl"); + + collect_register (regcache, mte_base, mte_regset); +} + +/* Store the MTE registers to regcache. */ + +static void +aarch64_store_mteregset (struct regcache *regcache, const void *buf) +{ + uint64_t *mte_regset = (uint64_t *) buf; + int mte_base = find_regno (regcache->tdesc, "tag_ctl"); + + /* Tag Control register */ + supply_register (regcache, mte_base, mte_regset); +} + bool aarch64_target::low_supports_breakpoints () { @@ -706,6 +729,9 @@ static struct regset_info aarch64_regsets[] = { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK, AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS, NULL, aarch64_store_pauthregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL, + AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset, + aarch64_store_mteregset }, NULL_REGSET }; @@ -735,6 +761,9 @@ static struct regset_info aarch64_sve_regsets[] = { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK, AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS, NULL, aarch64_store_pauthregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL, + AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset, + aarch64_store_mteregset }, NULL_REGSET }; diff --git a/include/elf/common.h b/include/elf/common.h index e7d55ae078..da911b8e18 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -672,6 +672,9 @@ /* note name must be "LINUX". */ #define NT_ARM_PAC_MASK 0x406 /* AArch pointer authentication code masks */ /* note name must be "LINUX". */ +#define NT_ARM_TAGGED_ADDR_CTRL 0x409 /* AArch64 tagged address control + (prctl()) */ + /* note name must be "LINUX". */ #define NT_ARC_V2 0x600 /* ARC HS accumulator/extra registers. */ /* note name must be "LINUX". */ #define NT_SIGINFO 0x53494749 /* Fields of siginfo_t. */ -- 2.25.1