From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id 1TdPITk9vl9cCgAAWB0awg (envelope-from ) for ; Wed, 25 Nov 2020 06:17:13 -0500 Received: by simark.ca (Postfix, from userid 112) id 747B81F0AB; Wed, 25 Nov 2020 06:17:13 -0500 (EST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=0.3 required=5.0 tests=MAILING_LIST_MULTI,RDNS_NONE, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from sourceware.org (unknown [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id D3CDE1E58E for ; Wed, 25 Nov 2020 06:17:12 -0500 (EST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 553DB3861972; Wed, 25 Nov 2020 11:17:12 +0000 (GMT) Received: from mx2.suse.de (mx2.suse.de [195.135.220.15]) by sourceware.org (Postfix) with ESMTPS id 8C4743861972 for ; Wed, 25 Nov 2020 11:17:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 8C4743861972 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=tdevries@suse.de X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 9DFE4AC41 for ; Wed, 25 Nov 2020 11:17:08 +0000 (UTC) Date: Wed, 25 Nov 2020 12:17:06 +0100 From: Tom de Vries To: gdb-patches@sourceware.org Subject: [PATCH][gdb/testsuite] Fix gdb.reverse/insn-reverse-x86.c for -m32 Message-ID: <20201125111705.GA1176@delia.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" Hi, When running test-case gdb.reverse/insn-reverse.exp with target board unix/-m32, we get: ... spawn -ignore SIGHUP gcc -fno-stack-protector -fdiagnostics-color=never \ -c -g -m32 -o insn-reverse0.o insn-reverse.c^M insn-reverse-x86.c: Assembler messages:^M insn-reverse-x86.c:88: Error: bad register name `%r8w'^M .... Fix this by guarding x86_64 assembly in insn-reverse-x86.c with #ifdef __x86_64__. Tested on x86_64-linux, with native and unix/-m32. Any comments? Thanks, - Tom [gdb/testsuite] Fix gdb.reverse/insn-reverse-x86.c for -m32 gdb/testsuite/ChangeLog: 2020-11-25 Tom de Vries * gdb.reverse/insn-reverse-x86.c: Guard x86_64 assembly with #ifdef __x86_64__. --- gdb/testsuite/gdb.reverse/insn-reverse-x86.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/gdb/testsuite/gdb.reverse/insn-reverse-x86.c b/gdb/testsuite/gdb.reverse/insn-reverse-x86.c index 22ba97a50d7..4392cb66def 100644 --- a/gdb/testsuite/gdb.reverse/insn-reverse-x86.c +++ b/gdb/testsuite/gdb.reverse/insn-reverse-x86.c @@ -85,6 +85,7 @@ rdrand (void) __asm__ volatile ("rdrand %%sp;" : "=r" (number)); __asm__ volatile ("mov %%ax, %%sp;" : "=r" (number)); +#ifdef __x86_64__ __asm__ volatile ("rdrand %%r8w;" : "=r" (number)); __asm__ volatile ("rdrand %%r9w;" : "=r" (number)); __asm__ volatile ("rdrand %%r10w;" : "=r" (number)); @@ -93,6 +94,7 @@ rdrand (void) __asm__ volatile ("rdrand %%r13w;" : "=r" (number)); __asm__ volatile ("rdrand %%r14w;" : "=r" (number)); __asm__ volatile ("rdrand %%r15w;" : "=r" (number)); +#endif /* 32-bit random numbers. */ __asm__ volatile ("rdrand %%eax;" : "=r" (number)); @@ -100,6 +102,7 @@ rdrand (void) __asm__ volatile ("rdrand %%ecx;" : "=r" (number)); __asm__ volatile ("rdrand %%edx;" : "=r" (number)); +#ifdef __x86_64__ __asm__ volatile ("mov %%rdi, %%rax;" : "=r" (number)); __asm__ volatile ("rdrand %%edi;" : "=r" (number)); __asm__ volatile ("mov %%rax, %%rdi;" : "=r" (number)); @@ -155,6 +158,7 @@ rdrand (void) __asm__ volatile ("rdrand %%r13;" : "=r" (number)); __asm__ volatile ("rdrand %%r14;" : "=r" (number)); __asm__ volatile ("rdrand %%r15;" : "=r" (number)); +#endif } /* Test rdseed support for various output registers. */ @@ -190,6 +194,7 @@ rdseed (void) __asm__ volatile ("rdseed %%sp;" : "=r" (seed)); __asm__ volatile ("mov %%ax, %%sp;" : "=r" (seed)); +#ifdef __x86_64__ __asm__ volatile ("rdseed %%r8w;" : "=r" (seed)); __asm__ volatile ("rdseed %%r9w;" : "=r" (seed)); __asm__ volatile ("rdseed %%r10w;" : "=r" (seed)); @@ -198,6 +203,7 @@ rdseed (void) __asm__ volatile ("rdseed %%r13w;" : "=r" (seed)); __asm__ volatile ("rdseed %%r14w;" : "=r" (seed)); __asm__ volatile ("rdseed %%r15w;" : "=r" (seed)); +#endif /* 32-bit random seeds. */ __asm__ volatile ("rdseed %%eax;" : "=r" (seed)); @@ -205,6 +211,7 @@ rdseed (void) __asm__ volatile ("rdseed %%ecx;" : "=r" (seed)); __asm__ volatile ("rdseed %%edx;" : "=r" (seed)); +#ifdef __x86_64__ __asm__ volatile ("mov %%rdi, %%rax;" : "=r" (seed)); __asm__ volatile ("rdseed %%edi;" : "=r" (seed)); __asm__ volatile ("mov %%rax, %%rdi;" : "=r" (seed)); @@ -260,6 +267,7 @@ rdseed (void) __asm__ volatile ("rdseed %%r13;" : "=r" (seed)); __asm__ volatile ("rdseed %%r14;" : "=r" (seed)); __asm__ volatile ("rdseed %%r15;" : "=r" (seed)); +#endif } /* Initialize arch-specific bits. */