From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id CB6vB/zkkV9pSAAAWB0awg (envelope-from ) for ; Thu, 22 Oct 2020 16:01:00 -0400 Received: by simark.ca (Postfix, from userid 112) id 1D75A1EFC7; Thu, 22 Oct 2020 16:01:00 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id D074D1E89B for ; Thu, 22 Oct 2020 16:00:52 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0FB0F398751D; Thu, 22 Oct 2020 20:00:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0FB0F398751D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1603396852; bh=j8WnA9+vUmvg6LuT7SMosVu6AA8cmJF9w+qPF7L71xk=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=axPmTT6Kw3+JdXoLBIKIFSlLM3SOEy87BUuSQfmlr62f31hNpFEAoRrcFd4rs2220 irdIMDqXDxVKuAcKMhp56Z1FQwKdyhHa+0yFyBaOXA3ZC5lxWxqOl6T1lqR75/T2Yw sikkpYfb05kyAlFy0bXEwqr3DZJyfYVD45YHHEoI= Received: from mail-qt1-x842.google.com (mail-qt1-x842.google.com [IPv6:2607:f8b0:4864:20::842]) by sourceware.org (Postfix) with ESMTPS id 430253987479 for ; Thu, 22 Oct 2020 20:00:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 430253987479 Received: by mail-qt1-x842.google.com with SMTP id c13so2244584qtx.6 for ; Thu, 22 Oct 2020 13:00:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j8WnA9+vUmvg6LuT7SMosVu6AA8cmJF9w+qPF7L71xk=; b=ZdUzUdrugxswYnsg++IZJ8PQVtq/z58bFw2Et8+PWKFUS+IfvfeBTRV21Qq2iOTgqF vmeJYksrFrB6qBpYN+jyfuudShttXJ7157zTq/KeinJm2cdwg0CPzwYn14olhcIYVj3M +U/Bj3y1UKAd5OmHt5UENRQ5hlGMFV1hme3kk8fN9NdCAV0chFLIGC4k56N/zM/qOywx RTIcgBv883mqglESvKEXdfA6WjfyozPb9Eoy/UBETd0Pf1ugquQDn0qhs+QeXvp+xLCt NdkdmrMP2slVYVbnnX+F3CGCrDmtd1EMp9gaiw76izBOTtEd3AyIsYWwd9kJUTePpRmP 2w/A== X-Gm-Message-State: AOAM5334TdbOziUIjjwpCOtDcWG/U2l3fHoQw0fOZmX7Zy+USmZN92/X iBFgdflM8PrVSBkqrP5mS9QysGZiSlCupA== X-Google-Smtp-Source: ABdhPJyL13f0yqauduiirkIBvEl6h8JB+IoAY73xKeVkK+C48aEn7BYeMjoonsZoQlIm1+wb7EcC4w== X-Received: by 2002:ac8:5c82:: with SMTP id r2mr3781350qta.195.1603396848381; Thu, 22 Oct 2020 13:00:48 -0700 (PDT) Received: from localhost.localdomain ([2804:7f0:8284:1487:b9b1:f72a:8f1:600]) by smtp.gmail.com with ESMTPSA id a21sm1711208qkk.98.2020.10.22.13.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 13:00:48 -0700 (PDT) To: gdb-patches@sourceware.org Subject: [PATCH v2 10/24] AArch64: Add MTE register set support for GDB and gdbserver Date: Thu, 22 Oct 2020 17:00:00 -0300 Message-Id: <20201022200014.5189-11-luis.machado@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201022200014.5189-1-luis.machado@linaro.org> References: <20201022200014.5189-1-luis.machado@linaro.org> X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Luis Machado via Gdb-patches Reply-To: Luis Machado Cc: david.spickett@linaro.org Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" AArch64 MTE support in the Linux kernel exposes a new register through ptrace. This patch adds the required code to support it. include/ChangeLog: YYYY-MM-DD Luis Machado * elf/common.h (NT_ARM_TAGGED_ADDR_CTRL): Define. gdb/ChangeLog: YYYY-MM-DD Luis Machado * aarch64-linux-nat.c (fetch_mteregs_from_thread): New function. (store_mteregs_to_thread): New function. (aarch64_linux_nat_target::fetch_registers): Update to call fetch_mteregs_from_thread. (aarch64_linux_nat_target::store_registers): Update to call store_mteregs_to_thread. * aarch64-tdep.c (aarch64_mte_register_names): New struct. (aarch64_cannot_store_register): Handle MTE registers. (aarch64_gdbarch_init): Initialize and setup MTE registers. * aarch64-tdep.h (gdbarch_tdep) : New field. : New method. * arch/aarch64-linux.h (AARCH64_LINUX_SIZEOF_MTE): Define. gdbserver/ChangeLog: YYYY-MM-DD Luis Machado * linux-aarch64-low.cc (aarch64_fill_mteregset): New function. (aarch64_store_mteregset): New function. (aarch64_regsets): Add MTE register set entry. (aarch64_sve_regsets): Add MTE register set entry. --- gdb/aarch64-linux-nat.c | 70 ++++++++++++++++++++++++++++++++++ gdb/aarch64-tdep.c | 24 ++++++++++++ gdb/aarch64-tdep.h | 9 +++++ gdb/arch/aarch64-mte-linux.h | 3 ++ gdbserver/linux-aarch64-low.cc | 29 ++++++++++++++ include/elf/common.h | 3 ++ 6 files changed, 138 insertions(+) diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c index 1392ec440c..dea34da669 100644 --- a/gdb/aarch64-linux-nat.c +++ b/gdb/aarch64-linux-nat.c @@ -461,6 +461,60 @@ fetch_pauth_masks_from_thread (struct regcache *regcache) &pauth_regset[1]); } +/* Fill GDB's register array with the MTE register values from + the current thread. */ + +static void +fetch_mteregs_from_thread (struct regcache *regcache) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + int regno = tdep->mte_reg_base; + + gdb_assert (regno != -1); + + uint64_t tag_ctl = 0; + struct iovec iovec; + + iovec.iov_base = &tag_ctl; + iovec.iov_len = sizeof (tag_ctl); + + int tid = regcache->ptid ().lwp (); + if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, + &iovec) != 0) + perror_with_name (_("unable to fetch MTE registers.")); + + regcache->raw_supply (regno, &tag_ctl); +} + +/* Store to the current thread the valid MTE register set in the GDB's + register array. */ + +static void +store_mteregs_to_thread (struct regcache *regcache) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + int regno = tdep->mte_reg_base; + + gdb_assert (regno != -1); + + uint64_t tag_ctl = 0; + + if (REG_VALID != regcache->get_register_status (regno)) + return; + + regcache->raw_collect (regno, (char *) &tag_ctl); + + struct iovec iovec; + + iovec.iov_base = &tag_ctl; + iovec.iov_len = sizeof (tag_ctl); + + int tid = regcache->ptid ().lwp (); + if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, + &iovec) != 0) + perror_with_name (_("unable to store MTE registers.")); +} + /* Implement the "fetch_registers" target_ops method. */ void @@ -479,6 +533,9 @@ aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, if (tdep->has_pauth ()) fetch_pauth_masks_from_thread (regcache); + + if (tdep->has_mte ()) + fetch_mteregs_from_thread (regcache); } else if (regno < AARCH64_V0_REGNUM) fetch_gregs_from_thread (regcache); @@ -493,6 +550,11 @@ aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)) fetch_pauth_masks_from_thread (regcache); } + + /* Fetch individual MTE registers. */ + if (tdep->has_mte () + && (regno == tdep->mte_reg_base)) + fetch_mteregs_from_thread (regcache); } /* Implement the "store_registers" target_ops method. */ @@ -510,6 +572,9 @@ aarch64_linux_nat_target::store_registers (struct regcache *regcache, store_sveregs_to_thread (regcache); else store_fpregs_to_thread (regcache); + + if (tdep->has_mte ()) + store_mteregs_to_thread (regcache); } else if (regno < AARCH64_V0_REGNUM) store_gregs_to_thread (regcache); @@ -517,6 +582,11 @@ aarch64_linux_nat_target::store_registers (struct regcache *regcache, store_sveregs_to_thread (regcache); else store_fpregs_to_thread (regcache); + + /* Store MTE registers. */ + if (tdep->has_mte () + && (regno == tdep->mte_reg_base)) + store_mteregs_to_thread (regcache); } /* Fill register REGNO (if it is a general-purpose register) in diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index d8b0e021ac..41a790ff0a 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -176,6 +176,12 @@ static const char *const aarch64_pauth_register_names[] = "pauth_cmask" }; +static const char *const aarch64_mte_register_names[] = +{ + /* Tag Control Register. */ + "tag_ctl" +}; + /* AArch64 prologue cache structure. */ struct aarch64_prologue_cache { @@ -3364,6 +3370,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) bool valid_p = true; int i, num_regs = 0, num_pseudo_regs = 0; int first_pauth_regnum = -1, pauth_ra_state_offset = -1; + int first_mte_regnum = -1; /* Use the vector length passed via the target info. Here -1 is used for no SVE, and 0 is unset. If unset then use the vector length from the existing @@ -3401,6 +3408,8 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu"); feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve"); feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth"); + const struct tdesc_feature *feature_mte + = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.mte"); if (feature_core == nullptr) return nullptr; @@ -3471,6 +3480,20 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */ } + /* Add the MTE registers. */ + if (feature_mte != NULL) + { + first_mte_regnum = num_regs; + /* Validate the descriptor provides the mandatory MTE registers and + allocate their numbers. */ + for (i = 0; i < ARRAY_SIZE (aarch64_mte_register_names); i++) + valid_p &= tdesc_numbered_register (feature_mte, tdesc_data.get (), + first_mte_regnum + i, + aarch64_mte_register_names[i]); + + num_regs += i; + } + if (!valid_p) return nullptr; @@ -3488,6 +3511,7 @@ aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->pauth_reg_base = first_pauth_regnum; tdep->pauth_ra_state_regnum = (feature_pauth == NULL) ? -1 : pauth_ra_state_offset + num_regs; + tdep->mte_reg_base = first_mte_regnum; set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call); set_gdbarch_frame_align (gdbarch, aarch64_frame_align); diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h index aa95e3c7bd..8ca299b362 100644 --- a/gdb/aarch64-tdep.h +++ b/gdb/aarch64-tdep.h @@ -100,6 +100,15 @@ struct gdbarch_tdep { return pauth_reg_base != -1; } + + /* First MTE register. This is -1 if no MTE registers are available. */ + int mte_reg_base; + + /* Returns true if the target supports MTE. */ + bool has_mte () const + { + return mte_reg_base != -1; + } }; const target_desc *aarch64_read_description (uint64_t vq, bool pauth_p, diff --git a/gdb/arch/aarch64-mte-linux.h b/gdb/arch/aarch64-mte-linux.h index c6a91c2db4..4124e80543 100644 --- a/gdb/arch/aarch64-mte-linux.h +++ b/gdb/arch/aarch64-mte-linux.h @@ -25,4 +25,7 @@ #define HWCAP2_MTE (1 << 18) #endif +/* The MTE regset consists of a single 64-bit register. */ +#define AARCH64_LINUX_SIZEOF_MTE 8 + #endif /* ARCH_AARCH64_LINUX_H */ diff --git a/gdbserver/linux-aarch64-low.cc b/gdbserver/linux-aarch64-low.cc index 60d60a4d5c..22485d9466 100644 --- a/gdbserver/linux-aarch64-low.cc +++ b/gdbserver/linux-aarch64-low.cc @@ -261,6 +261,29 @@ aarch64_store_pauthregset (struct regcache *regcache, const void *buf) &pauth_regset[1]); } +/* Fill BUF with the MTE registers from the regcache. */ + +static void +aarch64_fill_mteregset (struct regcache *regcache, void *buf) +{ + uint64_t *mte_regset = (uint64_t *) buf; + int mte_base = find_regno (regcache->tdesc, "tag_ctl"); + + collect_register (regcache, mte_base, mte_regset); +} + +/* Store the MTE registers to regcache. */ + +static void +aarch64_store_mteregset (struct regcache *regcache, const void *buf) +{ + uint64_t *mte_regset = (uint64_t *) buf; + int mte_base = find_regno (regcache->tdesc, "tag_ctl"); + + /* Tag Control register */ + supply_register (regcache, mte_base, mte_regset); +} + bool aarch64_target::low_supports_breakpoints () { @@ -684,6 +707,9 @@ static struct regset_info aarch64_regsets[] = { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK, AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS, NULL, aarch64_store_pauthregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL, + AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset, + aarch64_store_mteregset }, NULL_REGSET }; @@ -713,6 +739,9 @@ static struct regset_info aarch64_sve_regsets[] = { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK, AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS, NULL, aarch64_store_pauthregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL, + AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset, + aarch64_store_mteregset }, NULL_REGSET }; diff --git a/include/elf/common.h b/include/elf/common.h index b3c30e0e2f..6ed5b1cda2 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -660,6 +660,9 @@ /* note name must be "LINUX". */ #define NT_ARM_PAC_MASK 0x406 /* AArch pointer authentication code masks */ /* note name must be "LINUX". */ +#define NT_ARM_TAGGED_ADDR_CTRL 0x409 /* AArch64 tagged address control + (prctl()) */ + /* note name must be "LINUX". */ #define NT_ARC_V2 0x600 /* ARC HS accumulator/extra registers. */ /* note name must be "LINUX". */ #define NT_SIGINFO 0x53494749 /* Fields of siginfo_t. */ -- 2.17.1