From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by sourceware.org (Postfix) with ESMTPS id C78163858D35 for ; Fri, 31 Jul 2020 14:10:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org C78163858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=mittosystems.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=jozef.l@mittosystems.com Received: by mail-wr1-x435.google.com with SMTP id f7so28166602wrw.1 for ; Fri, 31 Jul 2020 07:10:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mittosystems.com; s=google; h=date:from:to:subject:message-id:mime-version:content-disposition; bh=OLsHzqtKG7Z6eaeCg9dqb9diDDO5sUPJawxZIa/TDeA=; b=F858fbQf9GA5DS/khRETnlY0g0GLv7N1k+Zp4V7xzs2cLnJuAUmsvk4G3fHoj7e36C GqKCf9bjjanCe+EpJbRPSGBm4hgqobrECTvVq6YK9Uo1GUc/WMitjG7RieDkovM/QNeW ztE/cKNckBWiYcLsl9YagtBCMwNM+OC+2mC38Q1t5cchTj1IbAeELwsjIWDeu8nSh/7y 1YotpFsj6kKFY3syOungiUauPqSbgnhhuZHCPUKkHMTCTf5qPR2ce+PcK37J11kCQXYW xS3JVsLnAzW6hJ0AQwZD2+9FqUr/om93Kr02bfXADPcKl7J/Syc0jbMnhOGnA/38yaCx RnzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:subject:message-id:mime-version :content-disposition; bh=OLsHzqtKG7Z6eaeCg9dqb9diDDO5sUPJawxZIa/TDeA=; b=l70wmkAJZOqKk7tqhMTNxVuo7jABDmq3wnCZ/PXdgqUC8c8JUZ87YheNtH43wKFAGd mF7xBH1BKZ1/fb35NvFbhkEVfRDioaSrTeBUz+YvW5HHB9Rdh3iwjxoWO6E+QIYvSIbT puPVB5164imZM1kMYVQ/7fcKxSCRh90v41iOH0UxvfEIloklKODGxPlu1m095Yvm+M9K aNeXXSI7Hrs2VoBG7gHHG62NRcAfpb/05UL6JiO7o5tXYdW90EEmV13ElqaVv53JX9kt one1ZJN9b/GE0tSretOKWR5Cbd7I9YeDokuaM9SCNY452NtJ8fXuVmwaul7ey7Gbu5ab eeIQ== X-Gm-Message-State: AOAM530x4+6vZ6Z79aZB8MA9k1/YJ6c+vYvDppozPOCI3EynPlq094H1 LNQisBQ06hDSZM19jP/jJo5U5jQbzJo= X-Google-Smtp-Source: ABdhPJyE69C/4d1hhl/N8xRskqK/DSSRwkDDgKNRiay8lOH77DRWoA/NmfE7yvNWlUbPZj8TH63ECg== X-Received: by 2002:a5d:558a:: with SMTP id i10mr3485931wrv.146.1596204621458; Fri, 31 Jul 2020 07:10:21 -0700 (PDT) Received: from jozef-acer-manjaro ([2a01:4b00:87fd:900:5e1d:5c99:56da:76e8]) by smtp.gmail.com with ESMTPSA id g14sm12500268wmk.37.2020.07.31.07.10.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2020 07:10:20 -0700 (PDT) Date: Fri, 31 Jul 2020 15:11:00 +0100 From: Jozef Lawrynowicz To: gdb-patches@sourceware.org Subject: [PATCH] MSP430: sim: Fix incorrect simulation of unsigned widening multiply Message-ID: <20200731141100.adrjos6aixi65r2y@jozef-acer-manjaro> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="un75p6prvlm3kg2o" Content-Disposition: inline X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 31 Jul 2020 14:10:25 -0000 --un75p6prvlm3kg2o Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Operand sizes used for simulation of MSP430 hardware multiply operations are not aligned with the sizes used on the target, resulting in the simulator storing signed operands with too much precision. Additionally, simulation of unsigned multiplication is missing explicit casts to prevent any implicit sign extension. gcc.c-torture/execute/pr91450-1.c uses unsigned widening multiplication of 32-bit operands -4 and 2, to a 64-bit result: 0xffff fffc * 0x2 = 0x1 ffff fff8 If -4 is stored in 64-bit precision, then the multiplication is essentially signed and the result is -8 in 64-bit precision (0xffff ffff ffff fffc), which is not correct. Successfully regtested the GCC and G++ DejaGNU testsuites for msp430-elf in the default configuration, and with -mhwmult=f5series. This patch fixes 158 execution failures for -mhwmult=f5series. Ok to apply? Thanks, Jozef --un75p6prvlm3kg2o Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="0001-MSP430-sim-Fix-incorrect-simulation-of-unsigned-wide.patch" >From 68a3cab29e116dc91a07add7ee16d19175db36a1 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Tue, 28 Jul 2020 10:36:10 +0100 Subject: [PATCH] MSP430: sim: Fix incorrect simulation of unsigned widening multiply Operand sizes used for simulation of MSP430 hardware multiply operations are not aligned with the sizes used on the target, resulting in the simulator storing signed operands with too much precision. Additionally, simulation of unsigned multiplication is missing explicit casts to prevent any implicit sign extension. gcc.c-torture/execute/pr91450-1.c uses unsigned widening multiplication of 32-bit operands -4 and 2, to a 64-bit result: 0xffff fffc * 0x2 = 0x1 ffff fff8 If -4 is stored in 64-bit precision, then the multiplication is essentially signed and the result is -8 in 64-bit precision (0xffff ffff ffff fffc), which is not correct. sim/msp430/ChangeLog: 2020-07-31 Jozef Lawrynowicz * msp430-sim.c (put_op): For unsigned multiplication, explicitly cast operands to the unsigned type before multiplying. * msp430-sim.h (struct msp430_cpu_state): Fix types used to store hwmult operands. --- sim/msp430/msp430-sim.c | 28 ++++++++++++++++++++-------- sim/msp430/msp430-sim.h | 8 ++++---- 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/sim/msp430/msp430-sim.c b/sim/msp430/msp430-sim.c index e21c8cf6a64..a330c6caf5d 100644 --- a/sim/msp430/msp430-sim.c +++ b/sim/msp430/msp430-sim.c @@ -566,8 +566,13 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val) switch (HWMULT (sd, hwmult_type)) { case UNSIGN_32: - HWMULT (sd, hwmult_result) = HWMULT (sd, hwmult_op1) * HWMULT (sd, hwmult_op2); - HWMULT (sd, hwmult_signed_result) = (signed) HWMULT (sd, hwmult_result); + a = HWMULT (sd, hwmult_op1); + b = HWMULT (sd, hwmult_op2); + /* For unsigned 32-bit multiplication of 16-bit operands, an + explicit cast is required to prevent any implicit + sign-extension. */ + HWMULT (sd, hwmult_result) = (unsigned32) a * (unsigned32) b; + HWMULT (sd, hwmult_signed_result) = a * b; HWMULT (sd, hwmult_accumulator) = HWMULT (sd, hwmult_signed_accumulator) = 0; break; @@ -575,13 +580,16 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val) a = sign_ext (HWMULT (sd, hwmult_op1), 16); b = sign_ext (HWMULT (sd, hwmult_op2), 16); HWMULT (sd, hwmult_signed_result) = a * b; - HWMULT (sd, hwmult_result) = (unsigned) HWMULT (sd, hwmult_signed_result); + HWMULT (sd, hwmult_result) = (unsigned32) a * (unsigned32) b; HWMULT (sd, hwmult_accumulator) = HWMULT (sd, hwmult_signed_accumulator) = 0; break; case UNSIGN_MAC_32: - HWMULT (sd, hwmult_accumulator) += HWMULT (sd, hwmult_op1) * HWMULT (sd, hwmult_op2); - HWMULT (sd, hwmult_signed_accumulator) += HWMULT (sd, hwmult_op1) * HWMULT (sd, hwmult_op2); + a = HWMULT (sd, hwmult_op1); + b = HWMULT (sd, hwmult_op2); + HWMULT (sd, hwmult_accumulator) + += (unsigned32) a * (unsigned32) b; + HWMULT (sd, hwmult_signed_accumulator) += a * b; HWMULT (sd, hwmult_result) = HWMULT (sd, hwmult_accumulator); HWMULT (sd, hwmult_signed_result) = HWMULT (sd, hwmult_signed_accumulator); break; @@ -589,7 +597,8 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val) case SIGN_MAC_32: a = sign_ext (HWMULT (sd, hwmult_op1), 16); b = sign_ext (HWMULT (sd, hwmult_op2), 16); - HWMULT (sd, hwmult_accumulator) += a * b; + HWMULT (sd, hwmult_accumulator) + += (unsigned32) a * (unsigned32) b; HWMULT (sd, hwmult_signed_accumulator) += a * b; HWMULT (sd, hwmult_result) = HWMULT (sd, hwmult_accumulator); HWMULT (sd, hwmult_signed_result) = HWMULT (sd, hwmult_signed_accumulator); @@ -648,10 +657,13 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val) switch (HWMULT (sd, hw32mult_type)) { case UNSIGN_64: - HWMULT (sd, hw32mult_result) = HWMULT (sd, hw32mult_op1) * HWMULT (sd, hw32mult_op2); + HWMULT (sd, hw32mult_result) + = (unsigned64) HWMULT (sd, hw32mult_op1) + * (unsigned64) HWMULT (sd, hw32mult_op2); break; case SIGN_64: - HWMULT (sd, hw32mult_result) = sign_ext (HWMULT (sd, hw32mult_op1), 32) + HWMULT (sd, hw32mult_result) + = sign_ext (HWMULT (sd, hw32mult_op1), 32) * sign_ext (HWMULT (sd, hw32mult_op2), 32); break; } diff --git a/sim/msp430/msp430-sim.h b/sim/msp430/msp430-sim.h index ad83e5b6ae6..7c486c2f350 100644 --- a/sim/msp430/msp430-sim.h +++ b/sim/msp430/msp430-sim.h @@ -31,16 +31,16 @@ struct msp430_cpu_state int cio_buffer; hwmult_type hwmult_type; - unsigned32 hwmult_op1; - unsigned32 hwmult_op2; + unsigned16 hwmult_op1; + unsigned16 hwmult_op2; unsigned32 hwmult_result; signed32 hwmult_signed_result; unsigned32 hwmult_accumulator; signed32 hwmult_signed_accumulator; hw32mult_type hw32mult_type; - unsigned64 hw32mult_op1; - unsigned64 hw32mult_op2; + unsigned32 hw32mult_op1; + unsigned32 hw32mult_op2; unsigned64 hw32mult_result; }; -- 2.27.0 --un75p6prvlm3kg2o--