From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by sourceware.org (Postfix) with ESMTPS id 3C639385040E for ; Thu, 23 Jul 2020 19:35:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 3C639385040E Received: by mail-ej1-x642.google.com with SMTP id f12so7591038eja.9 for ; Thu, 23 Jul 2020 12:35:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R5pfODmBap/MyXC7BPk7t5kaFXjEb/3G79+bSFFKOXA=; b=rz/yLZgRpRrnS4hYv0izM35L3KwYF0O468b22XljERAPx/sySbG/fC9+YG+Fcm6YDE vmFBHf0GxmlD9Moy1he4Onv0XOeUd2aFKeklf01ijDArxfZQE58OD+0ZEgBCVv772usF Xn3HYl56C52p3Byi54Xqbl8d04fRgeCj8rBitfzjJ+J+aADgl2jPbM6Tpg59i7V3KQk/ JN7hsbHfI9RHqgs5Dwm23JiMg2F8cGjvDWxPKdu051RngQ3/9UdFFPwYU/3XAqGCaUJ9 R/a4bpE3KfWHLQeBnBwigDDzbE3wsxpk7OPwTEo3/vMt8ukJNk2thDLyKqExzW1mPCp+ 9uQg== X-Gm-Message-State: AOAM531Vpn1pTnosUaJTBwCTmhFwQF3i9zRnlugcxbAvRyOKaWuFw4/P uYAnr5wztNED/9GWW5koHcJcbB0Kcg2XMQ== X-Google-Smtp-Source: ABdhPJxQFlVlXc49cGp3H+dyIb4bkH8f1lMytPAYBh1G+GlnW2x/TYthXd07jqBm+p0XQZeHMXnJNg== X-Received: by 2002:a17:906:3650:: with SMTP id r16mr5576531ejb.465.1595532945793; Thu, 23 Jul 2020 12:35:45 -0700 (PDT) Received: from atlantis.home ([2a03:1b20:3:f011::6d]) by smtp.gmail.com with ESMTPSA id cw14sm2702048edb.88.2020.07.23.12.35.44 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Jul 2020 12:35:45 -0700 (PDT) From: Shahab Vahedi To: gdb-patches@sourceware.org Cc: Shahab Vahedi , Shahab Vahedi , Simon Marchi , Tom Tromey , Anton Kolesov , Francois Bedard Subject: [PATCH v4 2/3] arc: Add hardware loop detection Date: Thu, 23 Jul 2020 21:35:31 +0200 Message-Id: <20200723193532.25812-3-shahab.vahedi@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200723193532.25812-1-shahab.vahedi@gmail.com> References: <20200713154527.13430-1-shahab.vahedi@gmail.com> <20200723193532.25812-1-shahab.vahedi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Jul 2020 19:35:48 -0000 From: Shahab Vahedi For ARC there are registers that are not part of a required set in XML target descriptions by default, but are almost always present on ARC targets and are universally exposed by the ptrace interface. Hardware loop registers being one of them. LP_START and LP_END auxiliary registers are hardware loop start and end. Formally, they are optional, but it is hard to find an ARC configuration that doesn't have them. They are always present in processors that can run GNU/Linux. GDB needs to know about those registers to implement proper software single stepping, since they affect what instruction will be next. This commit adds the code to check for the existance of "lp_start" and "lp_end" in XML target descriptions. If they exist, then the function reports that the target supports hardware loops. gdb/ChangeLog: 2020-07-22 Shahab Vahedi * arc-tdep.c (arc_check_for_hardware_loop): New. * arc-tdep.h (gdbarch_tdep): New field has_hw_loops. gdb/doc/ChangeLog: 2020-07-22 Anton Kolesov * gdb.texinfo (Synopsys ARC): Document LP_START, LP_END and BTA. --- gdb/arc-tdep.c | 39 +++++++++++++++++++++++++++++++++++---- gdb/arc-tdep.h | 4 ++++ gdb/doc/gdb.texinfo | 3 ++- 3 files changed, 41 insertions(+), 5 deletions(-) diff --git a/gdb/arc-tdep.c b/gdb/arc-tdep.c index 0c7e045e54b..59e698bb18b 100644 --- a/gdb/arc-tdep.c +++ b/gdb/arc-tdep.c @@ -2006,6 +2006,35 @@ arc_check_tdesc_feature (struct tdesc_arch_data *tdesc_data, return true; } +/* Check for the existance of "lp_start" and "lp_end" in target description. + If both are present, assume there is hardware loop support in the target. + This can be improved by looking into "lpc_size" field of "isa_config" + auxiliary register. */ + +static bool +arc_check_for_hw_loops (const struct target_desc *tdesc, + struct tdesc_arch_data *data) +{ + const auto feature_aux = tdesc_find_feature (tdesc, ARC_AUX_FEATURE_NAME); + const auto *aux_regset = determine_aux_reg_feature_set (); + + if (feature_aux == nullptr || aux_regset == nullptr) + return false; + + bool hw_loop_p = false; + const auto lp_start_name = + aux_regset->registers[ARC_LP_START_REGNUM - ARC_FIRST_AUX_REGNUM].names[0]; + const auto lp_end_name = + aux_regset->registers[ARC_LP_END_REGNUM - ARC_FIRST_AUX_REGNUM].names[0]; + + hw_loop_p = tdesc_numbered_register (feature_aux, data, + ARC_LP_START_REGNUM, lp_start_name); + hw_loop_p &= tdesc_numbered_register (feature_aux, data, + ARC_LP_END_REGNUM, lp_end_name); + + return hw_loop_p; +} + /* Initialize target description for the ARC. Returns true if input TDESC was valid and in this case it will assign TDESC @@ -2125,13 +2154,15 @@ arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) debug_printf ("arc: Architecture initialization.\n"); if (!arc_tdesc_init (info, &tdesc, &tdesc_data)) - return NULL; + return nullptr; /* Allocate the ARC-private target-dependent information structure, and the GDB target-independent information structure. */ - struct gdbarch_tdep *tdep = XCNEW (struct gdbarch_tdep); + gdb::unique_xmalloc_ptr tdep + (XCNEW (struct gdbarch_tdep)); tdep->jb_pc = -1; /* No longjmp support by default. */ - struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep); + tdep->has_hw_loops = arc_check_for_hw_loops (tdesc, tdesc_data); + struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep.release ()); /* Data types. */ set_gdbarch_short_bit (gdbarch, 16); @@ -2212,7 +2243,7 @@ arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) It can override functions set earlier. */ gdbarch_init_osabi (info, gdbarch); - if (tdep->jb_pc >= 0) + if (gdbarch_tdep (gdbarch)->jb_pc >= 0) set_gdbarch_get_longjmp_target (gdbarch, arc_get_longjmp_target); /* Disassembler options. Enforce CPU if it was specified in XML target diff --git a/gdb/arc-tdep.h b/gdb/arc-tdep.h index 6ca759a661d..e752348a262 100644 --- a/gdb/arc-tdep.h +++ b/gdb/arc-tdep.h @@ -23,6 +23,7 @@ /* Need disassemble_info. */ #include "dis-asm.h" +#include "gdbarch.h" #include "arch/arc.h" /* To simplify GDB code this enum assumes that internal regnums should be same @@ -110,6 +111,9 @@ struct gdbarch_tdep /* Offset to PC value in jump buffer. If this is negative, longjmp support will be disabled. */ int jb_pc; + + /* Whether target has hardware (aka zero-delay) loops. */ + bool has_hw_loops; }; /* Utility functions used by other ARC-specific modules. */ diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index a002084d5b9..9502992b9af 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -45238,7 +45238,8 @@ difference with @samp{org.gnu.gdb.arc.core.v2} feature is in the names of ARC v2, but @samp{ilink2} is optional on ARCompact. The @samp{org.gnu.gdb.arc.aux-minimal} feature is required for all ARC -targets. It should contain registers @samp{pc} and @samp{status32}. +targets. It should contain registers @samp{pc} and @samp{status32}. It may +contain registers @samp{lp_start}, @samp{lp_end} and @samp{bta}. @node ARM Features @subsection ARM Features -- 2.27.0