From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from hqnvemgate26.nvidia.com (hqnvemgate26.nvidia.com [216.228.121.65]) by sourceware.org (Postfix) with ESMTPS id 97B8E396E811 for ; Wed, 24 Jun 2020 01:29:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 97B8E396E811 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 23 Jun 2020 18:28:57 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 23 Jun 2020 18:29:09 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 23 Jun 2020 18:29:09 -0700 Received: from nvbus.nvidia.com (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 24 Jun 2020 01:29:09 +0000 From: Victor Collod To: Subject: [PATCH v3 6/7] amd64_analyze_prologue: fix incorrect comment Date: Tue, 23 Jun 2020 18:28:56 -0700 Message-ID: <20200624012857.31849-7-vcollod@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200624012857.31849-1-vcollod@nvidia.com> References: <0cc93067-1313-6434-4330-61a21736376f@simark.ca> <20200624012857.31849-1-vcollod@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Jun 2020 01:29:11 -0000 The width of the instruction didn't match the size of its operands. 2020-06-23 Victor Collod * amd64-tdep.c (amd64_analyze_prologue): Fix incorrect comment. --- gdb/amd64-tdep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index 5c3ad505784..901733cf443 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -2434,7 +2434,7 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, return pc; } =20 - /* For X32, also check for `movq %esp, %ebp'. */ + /* For X32, also check for `movl %esp, %ebp'. */ if (gdbarch_ptr_bit (gdbarch) =3D=3D 32) { if (memcmp (buf, mov_esp_ebp_1, 2) =3D=3D 0 --=20 2.20.1