From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from hqnvemgate26.nvidia.com (hqnvemgate26.nvidia.com [216.228.121.65]) by sourceware.org (Postfix) with ESMTPS id DB972396EC88 for ; Wed, 24 Jun 2020 01:29:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org DB972396EC88 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 23 Jun 2020 18:28:57 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 23 Jun 2020 18:29:09 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 23 Jun 2020 18:29:09 -0700 Received: from nvbus.nvidia.com (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 24 Jun 2020 01:29:09 +0000 From: Victor Collod To: Subject: [PATCH v3 5/7] amd64_analyze_prologue: gradually update pc Date: Tue, 23 Jun 2020 18:28:55 -0700 Message-ID: <20200624012857.31849-6-vcollod@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200624012857.31849-1-vcollod@nvidia.com> References: <0cc93067-1313-6434-4330-61a21736376f@simark.ca> <20200624012857.31849-1-vcollod@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Jun 2020 01:29:12 -0000 It makes the function easier to read, as you don't have to remember what's the current offset from pc. 2020-06-23 Victor Collod * amd64-tdep.c (amd64_analyze_prologue): Gradually update pc. --- gdb/amd64-tdep.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index 17b02706e54..5c3ad505784 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -2416,19 +2416,22 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, cache->saved_regs[AMD64_RBP_REGNUM] =3D 0; cache->sp_offset +=3D 8; =20 + pc +=3D 1; + /* If we went past the allowed bound, stop. */ - if (pc + 1 >=3D current_pc) + if (pc >=3D current_pc) return current_pc; =20 - read_code (pc + 1, buf, 3); + read_code (pc, buf, 3); =20 /* Check for `movq %rsp, %rbp'. */ if (memcmp (buf, mov_rsp_rbp_1, 3) =3D=3D 0 || memcmp (buf, mov_rsp_rbp_2, 3) =3D=3D 0) { + pc +=3D 3; /* OK, we actually have a frame. */ cache->frameless_p =3D 0; - return pc + 4; + return pc; } =20 /* For X32, also check for `movq %esp, %ebp'. */ @@ -2437,13 +2440,14 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, if (memcmp (buf, mov_esp_ebp_1, 2) =3D=3D 0 || memcmp (buf, mov_esp_ebp_2, 2) =3D=3D 0) { + pc +=3D 2; /* OK, we actually have a frame. */ cache->frameless_p =3D 0; - return pc + 3; + return pc; } } =20 - return pc + 1; + return pc; } =20 /* Work around false termination of prologue - GCC PR debug/48827. --=20 2.20.1