From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14549 invoked by alias); 22 Jan 2020 21:57:08 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 14541 invoked by uid 89); 22 Jan 2020 21:57:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=H*r:2a01, D*FreeBSD.org, setc X-HELO: mail-wm1-f52.google.com Received: from mail-wm1-f52.google.com (HELO mail-wm1-f52.google.com) (209.85.128.52) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Jan 2020 21:57:06 +0000 Received: by mail-wm1-f52.google.com with SMTP id q9so324286wmj.5 for ; Wed, 22 Jan 2020 13:57:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mittosystems.com; s=google; h=date:from:to:subject:message-id:mime-version; bh=1G29YaEC8SrxeatN4pFjC8YwlBMP+URacPJrOVivkfA=; b=klIi15zVyxnrgw29WLBZOQA5igegvt1OQDEtcrV0RBcMqoVAWFdO4Xal/NMdf33K7m HQx2L9l46sxX9ncXi+pr6yaBL4tDNnQi4CGL+LpIbKqZiRUbIIxzU7/JwNI/xgSS6jp4 rBA5ZEICa5Xk6SsrTi8Yww8RspLQ2j5kjT2cH1+UcMLd+r3JjBic8P5X0RIi3rh1NOAr 1JCXjSrOvpKnOo3Niu4OH1fSYlPhb3Fo+6d+EpidLr9s4rtRrMCEE3VXoxhbq873Qi3z cKMPcb89VQGVWc0cwsUmcUm1/UkkWFs5Lhiw7ZR+Zstlukqf67u7FhovXjiM5RDdmLHe 2IgA== Return-Path: Received: from jozef-kubuntu ([2a01:4b00:87fd:900:c952:cd3f:9ece:7039]) by smtp.gmail.com with ESMTPSA id z11sm13659wmg.30.2020.01.22.13.57.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Jan 2020 13:57:03 -0800 (PST) Date: Thu, 23 Jan 2020 00:57:00 -0000 From: Jozef Lawrynowicz To: gdb-patches@sourceware.org Subject: [COMMITTED][MSP430][SIM] Fix simulation of RRUX instruction Message-ID: <20200122215700.36914a84@jozef-kubuntu> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="MP_/lKRpwTVLQzNEkSDpd6go_uh" X-SW-Source: 2020-01/txt/msg00688.txt.bz2 --MP_/lKRpwTVLQzNEkSDpd6go_uh Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Disposition: inline Content-length: 757 The MSP430X RRUX instruction (unsigned right shift) is synthesized as the RRC (rotate right through carry) instruction, but with the ZC (zero carry) bit of the opcode extention word set. However, the simulator does not check the ZC bit before executing RRC, which leads to incorrect simulation of RRUX, if the carry bit in the status register happens to be set. The attached patch fixes this by modifying the simulation of RRC, so a 1 is only shifted into the MSB of the destination if the ZC bit of the extension word is clear AND the carry bit of the status register is set. I successfully regtested the GCC testsuite for msp430-elf, and this also fixed gcc.c-torture/execute/20020108-1.c which was executing incorrectly at -O0. Committed as obvious. --MP_/lKRpwTVLQzNEkSDpd6go_uh Content-Type: text/x-patch Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=0001-MSP430-Fix-simulator-execution-of-RRUX-instruction.patch Content-length: 3091 >From b7dcc42dfde12c3a1ccb7149b3cf8ef2f0992ea3 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Wed, 22 Jan 2020 21:44:54 +0000 Subject: [PATCH] MSP430: Fix simulator execution of RRUX instruction The MSP430X RRUX instruction (unsigned right shift) is synthesized as the RRC (rotate right through carry) instruction, but with the ZC (zero carry) bit of the opcode extention word set. Ensure the carry flag is ignored when the ZC bit is set. sim/msp430/ChangeLog: 2020-01-22 Jozef Lawrynowicz * msp430-sim.c (msp430_step_once): Ignore the carry flag when executing an RRC instruction, if the ZC bit of the extension word is set. sim/testsuite/sim/msp430/ChangeLog: 2020-01-22 Jozef Lawrynowicz * rrux.s: New test. --- sim/msp430/ChangeLog | 5 +++++ sim/msp430/msp430-sim.c | 6 ++++-- sim/testsuite/sim/msp430/ChangeLog | 4 ++++ sim/testsuite/sim/msp430/rrux.s | 14 ++++++++++++++ 4 files changed, 27 insertions(+), 2 deletions(-) create mode 100644 sim/testsuite/sim/msp430/rrux.s diff --git a/sim/msp430/ChangeLog b/sim/msp430/ChangeLog index 324a6fcaf1..0f27982068 100644 --- a/sim/msp430/ChangeLog +++ b/sim/msp430/ChangeLog @@ -1,3 +1,8 @@ +2020-01-22 Jozef Lawrynowicz + + * msp430-sim.c (msp430_step_once): Ignore the carry flag when executing + an RRC instruction, if the ZC bit of the extension word is set. + 2017-09-06 John Baldwin * configure: Regenerate. diff --git a/sim/msp430/msp430-sim.c b/sim/msp430/msp430-sim.c index cdb8eab71f..e21c8cf6a6 100644 --- a/sim/msp430/msp430-sim.c +++ b/sim/msp430/msp430-sim.c @@ -1292,8 +1292,10 @@ msp430_step_once (SIM_DESC sd) u1 = SRC; carry_to_use = u1 & 1; uresult = u1 >> 1; - if (SR & MSP430_FLAG_C) - uresult |= (1 << (opcode->size - 1)); + /* If the ZC bit of the opcode is set, it means we are synthesizing + RRUX, so the carry bit must be ignored. */ + if (opcode->zc == 0 && (SR & MSP430_FLAG_C)) + uresult |= (1 << (opcode->size - 1)); TRACE_ALU (MSP430_CPU (sd), "RRC: %#x >>= %#x", u1, uresult); DEST (uresult); diff --git a/sim/testsuite/sim/msp430/ChangeLog b/sim/testsuite/sim/msp430/ChangeLog index 458ee21873..7dc370f0a4 100644 --- a/sim/testsuite/sim/msp430/ChangeLog +++ b/sim/testsuite/sim/msp430/ChangeLog @@ -1,3 +1,7 @@ +2020-01-22 Jozef Lawrynowicz + + * rrux.s: New test. + 2016-01-05 Nick Clifton * testutils.inc (__pass): Use the LMA addresses of the _passmsg diff --git a/sim/testsuite/sim/msp430/rrux.s b/sim/testsuite/sim/msp430/rrux.s new file mode 100644 index 0000000000..07fc8d5a8d --- /dev/null +++ b/sim/testsuite/sim/msp430/rrux.s @@ -0,0 +1,14 @@ +# check that rrux (synthesized as rrc with ZC bit set) works. +# mach: msp430 + +.include "testutils.inc" + + start + + setc ; set the carry bit to ensure ZC bit is obeyed + mov.w #16, r10 + rrux.w r10 + cmp.w #8, r10 + jeq 1f + fail + 1: pass -- 2.17.1 --MP_/lKRpwTVLQzNEkSDpd6go_uh--