The MSP430X RRUX instruction (unsigned right shift) is synthesized as the RRC
(rotate right through carry) instruction, but with the ZC (zero carry) bit of
the opcode extention word set.

However, the simulator does not check the ZC bit before executing RRC, which
leads to incorrect simulation of RRUX, if the carry bit in the status register
happens to be set.

The attached patch fixes this by modifying the simulation of RRC, so a 1 is only
shifted into the MSB of the destination if the ZC bit of the extension word is
clear AND the carry bit of the status register is set.

I successfully regtested the GCC testsuite for msp430-elf, and this also fixed
gcc.c-torture/execute/20020108-1.c which was executing incorrectly at -O0.

Committed as obvious.