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From: Joel Brobecker <brobecker@adacore.com>
To: Andrew Burgess <andrew.burgess@embecosm.com>
Cc: Tom Tromey <tom@tromey.com>,
	gdb-patches@sourceware.org,	jimw@sifive.com, palmer@sifive.com,
	jhb@FreeBSD.org
Subject: Re: [PATCH] gdb/riscv: Add target description support
Date: Tue, 26 Feb 2019 11:55:00 -0000	[thread overview]
Message-ID: <20190226115510.GA22983@adacore.com> (raw)
In-Reply-To: <20190223203958.GA15942@embecosm.com>

Hi Andrew,

> [PATCH] gdb/riscv: Use legacy register numbers in default target description
> 
> When the target description support was added to RISC-V, the register
> numbers assigned to the fflags, frm, and fcsr control registers in the
> default target descriptions didn't match the register numbers used by
> GDB before the target description support was added.
> 
> What this means is that if a tools exists in the wild that is using
> hard-coded register number, setup to match GDB's old behaviour, then
> this will have been broken (for fflags, frm, and fcsr) by the move to
> target descriptions.  QEMU is such a tool.
> 
> There are a couple of solutions that could be used to work around this
> issue:
> 
>  - The user can create their own xml description file with the
>    register numbers setup to match their old tool, then load this by
>    telling GDB 'set tdesc filename FILENAME'.
> 
>  - Update their old tool to use the newer default numbering scheme, or
>    better yet add proper target description support to their tool.
> 
>  - We could have RISC-V GDB change to maintain the old defaults.
> 
> This patch implements the last of these ideas, changing the default
> numbering to match the old behaviour.
> 
> This change is only visible to targets that don't supply their own xml
> description file and instead rely on GDB's default numbering.
> 
> gdb/ChangeLog:
> 
> 	* features/riscv/32bit-cpu.xml: Add register numbers.
> 	* features/riscv/32bit-fpu.c: Regenerate.
> 	* features/riscv/32bit-fpu.xml: Add register numbers.
> 	* features/riscv/64bit-cpu.xml: Add register numbers.
> 	* features/riscv/64bit-fpu.c: Regenerate.
> 	* features/riscv/64bit-fpu.xml: Add register numbers.

I've had a chance to look at the patch, and fwiw, it looks good to me.
If others agree that it is OK, I think it would be nice if we pushed
the patch before I create the gdb-8.3-branch, and then create the first
pre-release (8.2.90).

-- 
Joel


  reply	other threads:[~2019-02-26 11:55 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-08 16:08 [RFC] " Andrew Burgess
2018-11-08 18:33 ` John Baldwin
2018-11-08 19:32   ` Palmer Dabbelt
2018-11-08 19:41     ` John Baldwin
2018-11-14 14:29   ` Andrew Burgess
2018-11-14 17:42     ` John Baldwin
2018-11-08 21:57 ` Jim Wilson
2018-11-13 15:05   ` Andrew Burgess
2018-11-13 20:08 ` Pedro Alves
2018-11-14 14:58 ` [PATCH] " Andrew Burgess
2018-11-19  3:51   ` Jim Wilson
2018-11-21 11:23     ` Andrew Burgess
2018-11-21 12:37       ` Eli Zaretskii
2018-11-21 13:19         ` Andrew Burgess
2019-02-22 17:42   ` Tom Tromey
2019-02-22 19:24     ` Jim Wilson
2019-02-23 20:51       ` Andrew Burgess
2019-02-24  6:21         ` Jim Wilson
2019-02-26  5:02           ` Joel Brobecker
2019-02-26 17:26             ` Jim Wilson
2019-02-26 18:22               ` Andrew Burgess
2019-02-26 18:40                 ` Jim Wilson
2019-02-26 19:27                   ` Jim Wilson
2019-02-26 20:30                     ` Andrew Burgess
2019-02-23 20:40     ` Andrew Burgess
2019-02-26 11:55       ` Joel Brobecker [this message]
2019-03-04 16:18       ` Tom Tromey

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