From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 127292 invoked by alias); 8 Feb 2019 10:32:01 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 127265 invoked by uid 89); 8 Feb 2019 10:32:00 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=jim, Wilson, Jim X-HELO: mail-wm1-f65.google.com Received: from mail-wm1-f65.google.com (HELO mail-wm1-f65.google.com) (209.85.128.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 08 Feb 2019 10:31:59 +0000 Received: by mail-wm1-f65.google.com with SMTP id p6so2834092wmc.1 for ; Fri, 08 Feb 2019 02:31:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=2MVhQCfZP9e1PJr8SHRYSuyrEi+iSoBV4VyjUVYkR3s=; b=AN6johIkHEqQTKw3AlLK9G57PJlTmWE5/LGS9FYiGHJj2peG0Ch8h0vtGCYr8cMsuy 2NQvutoT6araoKeRVtliUCadNjV50Ie7TFWuz+jObhcxpqkrnoPwWl+Xq5XXqJ6v/9Lg E4IgRgceyFCHOQEiTd4xqCoY3UxDpqR62DvHbJE/Uge5Ybnm/mbqlmd44fEJPN13dJVv 48ICOo0fIEuTNlOAxLIJSBjSep7aA1Qs+qb8tJDqW60dksTiAo6coMiFBa6sw1G73G06 79tg1ykpouJ6PtUVyMVHW3kRlw3MKAbC2pxANmZxLsAajl1AakPLl/ojGK34Rz0YCJXl LxRQ== Return-Path: Received: from localhost (host81-151-161-9.range81-151.btcentralplus.com. [81.151.161.9]) by smtp.gmail.com with ESMTPSA id b13sm2004719wrn.28.2019.02.08.02.31.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 02:31:56 -0800 (PST) Date: Fri, 08 Feb 2019 10:32:00 -0000 From: Andrew Burgess To: Jim Wilson Cc: gdb-patches@sourceware.org Subject: Re: [PATCH] RISC-V: Add FP register core file support. Message-ID: <20190208103155.GJ2829@embecosm.com> References: <20190206182424.2868-1-jimw@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190206182424.2868-1-jimw@sifive.com> X-Fortune: Mistakes are often the stepping stones to utter failure. X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] User-Agent: Mutt/1.9.2 (2017-12-15) X-IsSubscribed: yes X-SW-Source: 2019-02/txt/msg00079.txt.bz2 * Jim Wilson [2019-02-06 10:24:24 -0800]: > This adds fp reg support similar to the existing general reg support. > > This fixes one gdb testsuite failure > FAIL: gdb.base/gcore.exp: corefile restored system registers > which fails without the patch because fcsr was missing. Otherwise, no > regressions with riscv64-linux native testsuite run. > > gdb/ > * riscv-linux-tdep.c (riscv_linux_fregmap): New. > (riscv_linux_fregset): New. > (riscv_linux_iterate_over_regset_sections): Call cb for .reg2 > section. Looks good to me. Thanks, Andrew > --- > gdb/riscv-linux-tdep.c | 23 +++++++++++++++++++++-- > 1 file changed, 21 insertions(+), 2 deletions(-) > > diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c > index e1f8e76567..91061c5b3e 100644 > --- a/gdb/riscv-linux-tdep.c > +++ b/gdb/riscv-linux-tdep.c > @@ -37,6 +37,16 @@ static const struct regcache_map_entry riscv_linux_gregmap[] = > { 0 } > }; > > +/* Define the FP register mapping. The kernel puts the 32 FP regs first, and > + then FCSR. */ > + > +static const struct regcache_map_entry riscv_linux_fregmap[] = > +{ > + { 32, RISCV_FIRST_FP_REGNUM, 0 }, > + { 1, RISCV_CSR_FCSR_REGNUM, 0 }, > + { 0 } > +}; > + > /* Define the general register regset. */ > > static const struct regset riscv_linux_gregset = > @@ -44,6 +54,13 @@ static const struct regset riscv_linux_gregset = > riscv_linux_gregmap, regcache_supply_regset, regcache_collect_regset > }; > > +/* Define the FP register regset. */ > + > +static const struct regset riscv_linux_fregset = > +{ > + riscv_linux_fregmap, regcache_supply_regset, regcache_collect_regset > +}; > + > /* Define hook for core file support. */ > > static void > @@ -54,8 +71,10 @@ riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, > { > cb (".reg", (32 * riscv_isa_xlen (gdbarch)), (32 * riscv_isa_xlen (gdbarch)), > &riscv_linux_gregset, NULL, cb_data); > - > - /* TODO: Add FP register support. */ > + /* The kernel is adding 8 bytes for FCSR. */ > + cb (".reg2", (32 * riscv_isa_flen (gdbarch)) + 8, > + (32 * riscv_isa_flen (gdbarch)) + 8, > + &riscv_linux_fregset, NULL, cb_data); > } > > /* Signal trampoline support. */ > -- > 2.17.1 >