From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32304 invoked by alias); 13 Dec 2018 09:53:06 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 32290 invoked by uid 89); 13 Dec 2018 09:53:05 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=Wilson X-HELO: mail-wr1-f65.google.com Received: from mail-wr1-f65.google.com (HELO mail-wr1-f65.google.com) (209.85.221.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 13 Dec 2018 09:53:04 +0000 Received: by mail-wr1-f65.google.com with SMTP id t6so1122911wrr.12 for ; Thu, 13 Dec 2018 01:53:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=KwEx65Ay+5960o+9T1js06C5cv+MiXMbJvR2vtsILME=; b=ciLF9TG/cxgdsblD4+Hmf9LxlL7fcJwFaq66Dh4C33618/Z9YnkGTr2MKeLr36ziVa bxzwgLcLq9sR5buWbowrCHJ/BhFpMqKZ4CyRclz3BJwBsM/xBpN6Achzm0puovv1te9/ i0AXJ2dtMSjJayOF6R+0tFaCdjK8ozg7I+CYnhmwMpC4VIIR1ALcWiC85yCYKZ1GB2YT STjBFWE2++GCcEdQovKEhEvxT+rXRnnzKUp1PkPQ/BAOyhpCoO1zRRSq/s+fOsKZw/Ep aSIHPrAe9RwfHDCgAhR+nvVy2262Hdu8WWzsHfju56tcrheM8XvrY+jlSQqSj9eaP71y joLg== Return-Path: Received: from localhost ([2a02:390:741d:1:3665:d267:b319:d766]) by smtp.gmail.com with ESMTPSA id g16sm702901wru.41.2018.12.13.01.53.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Dec 2018 01:53:00 -0800 (PST) Date: Thu, 13 Dec 2018 09:53:00 -0000 From: Andrew Burgess To: Jim Wilson Cc: gdb-patches@sourceware.org Subject: Re: [PATCH] RISC-V: Correct printing of MSTATUS and MISA. Message-ID: <20181213095259.GN18841@embecosm.com> References: <20181213024943.15628-1-jimw@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181213024943.15628-1-jimw@sifive.com> X-Fortune: You're at Witt's End. X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] User-Agent: Mutt/1.9.2 (2017-12-15) X-IsSubscribed: yes X-SW-Source: 2018-12/txt/msg00144.txt.bz2 * Jim Wilson [2018-12-12 18:49:43 -0800]: > With my proposed qemu patches to make the RISC-V qemu gdbstub support work, > I noticed that a 64-bit MISA was printing wrong. "info registers misa" would > give me RV16ACDFIMSU. The problem here is that the MXL field is always in the > upper two bits of the register, but the code assumes it is in bits 31 and 30, > which is only correct for a 32-bit target. I copied code from the MSTATUS > support to fix this, and also noticed a bug in it. register_size returns > size in bytes, so we have to multiply by 8 to get size in bits. > > Tested by hand with qemu with my gdbstub patches applied, for both 32-bit and > 64-bit targets, printing MISA and verifying I get the right result back. Also > testing with a riscv64-linux gdb make check, with no regressions, though that > only proves I didn't break anything, since a user mode gdb can't read machine > registers. > > OK? > > Jim > > gdb/ > * riscv-tdep.c (riscv_print_one_register_info): For MSTATUS, add > comment for SD field, and correct xlen calculation. For MISA, add > comment for MXL field, add call to register_size, and correct base > calculation. Looks good to me. Thanks, Andrew > --- > gdb/riscv-tdep.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c > index 5ddec70307..41b6de1c4e 100644 > --- a/gdb/riscv-tdep.c > +++ b/gdb/riscv-tdep.c > @@ -701,8 +701,10 @@ riscv_print_one_register_info (struct gdbarch *gdbarch, > int size = register_size (gdbarch, regnum); > unsigned xlen; > > + /* The SD field is always in the upper bit of MSTATUS, regardless > + of the number of bits in MSTATUS. */ > d = value_as_long (val); > - xlen = size * 4; > + xlen = size * 8; > fprintf_filtered (file, > "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " > "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " > @@ -731,9 +733,13 @@ riscv_print_one_register_info (struct gdbarch *gdbarch, > int base; > unsigned xlen, i; > LONGEST d; > + int size = register_size (gdbarch, regnum); > > + /* The MXL field is always in the upper two bits of MISA, > + regardless of the number of bits in MISA. Mask out other > + bits to ensure we have a positive value. */ > d = value_as_long (val); > - base = d >> 30; > + base = (d >> ((size * 8) - 2)) & 0x3; > xlen = 16; > > for (; base > 0; base--) > -- > 2.17.1 >