From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29614 invoked by alias); 3 Nov 2018 08:35:01 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 29587 invoked by uid 89); 3 Nov 2018 08:35:00 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=MISA, misa X-HELO: mail-wm1-f65.google.com Received: from mail-wm1-f65.google.com (HELO mail-wm1-f65.google.com) (209.85.128.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 03 Nov 2018 08:34:58 +0000 Received: by mail-wm1-f65.google.com with SMTP id f1-v6so2655630wmg.1 for ; Sat, 03 Nov 2018 01:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=0gQz1Js15eGnsMyvuB2hZ7e00rK5/hTtx4fCmx4itNg=; b=IoIa8XwjTByOHQVqNHCQYi/9ORODPLcCUDELSYNKIF34hQzt8LJHSg2ZqT3AUHi1iS NIkctCPbtHGCA5yTZd+oDxoTMdMDfM3iySm7Ru+6ZLkpNHgWyr8eC7zQdUlMMW8qcfkR 8ij6Exryq75UpsqCymWWUAe4BQc2rStly9YUnlkqexxKv5lWfEmgQbuURGh8mOPzJFMv BpbzefRF5E3o9XYb2wj7RDhKVvI7oM/YcQWA/DdI1qZ7r/oNS4m6IhiVU+HsMeFRLa3d eNwdbKBNDPeReI/5jTwI/6Gu6Y3uy3mmFxAzbHoM7m/CtJ1d3y9aUG1eGcz8d2WLu6Or iCnw== Return-Path: Received: from localhost (host81-148-252-35.range81-148.btcentralplus.com. [81.148.252.35]) by smtp.gmail.com with ESMTPSA id x197-v6sm37041507wme.15.2018.11.03.01.34.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 03 Nov 2018 01:34:55 -0700 (PDT) Date: Sat, 03 Nov 2018 08:35:00 -0000 From: Andrew Burgess To: Jim Wilson Cc: gdb-patches@sourceware.org Subject: Re: [PATCH] RISC-V: Fix xlen to flen typo in FP reg handling. Message-ID: <20181103083453.GE16539@embecosm.com> References: <20181103032033.21653-1-jimw@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20181103032033.21653-1-jimw@sifive.com> X-Fortune: If you're not part of the solution, you're part of the precipitate. X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] User-Agent: Mutt/1.9.2 (2017-12-15) X-IsSubscribed: yes X-SW-Source: 2018-11/txt/msg00025.txt.bz2 * Jim Wilson [2018-11-02 20:20:33 -0700]: > This fixes a bug in FP register handling for targets where xlen != flen. > Tested against riscv-test/debug where it fixes a few failures. Also tested > on RV64GC linux with the gdb testsuite where it has no effect. > > gdb/ > * riscv-tdep.c (riscv_register_type): Use riscv_isa_flen for FP regs > not riscv_isa_xlen. Can you hold off merging this patch please. There's a non-obvious reason why this uses xlen here (even though it's the wrong thing to do). The reason is something to do with remote targets, when the remote target reads a register then it initialises a cache that contains the types of all registers (for the sizes I think), for FP regs right now, that results in a call to read MISA. This read requires the remote to initialise a cache of all the register types, which results in a read of MISA. Which requires the remote to initialise a cache ..... So we get stuck in infinite recursion :-( I'm pretty sure the above is basically correct, but I'd have to do some additional tests to get an exact explanation for you. However, don't worry. I'm currently working on proper target description support. I had hoped to get it posted this week, but it now looks like it will be early next week. I just need final testing and a bit of cleanup / ChangeLogs writing etc. The target description patch removes the MISA reading stuff completely right now, and fixes this xreg instead of freg hack. So could I ask, please don't push this until say the end of next week. If I haven't posted the target description patch by then, then go ahead and I'll accept that my remote tests will break. Thanks, Andrew > --- > gdb/riscv-tdep.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c > index db372e2163..b94802aa97 100644 > --- a/gdb/riscv-tdep.c > +++ b/gdb/riscv-tdep.c > @@ -630,7 +630,7 @@ riscv_register_type (struct gdbarch *gdbarch, int regnum) > } > else if (regnum <= RISCV_LAST_FP_REGNUM) > { > - regsize = riscv_isa_xlen (gdbarch); > + regsize = riscv_isa_flen (gdbarch); > switch (regsize) > { > case 4: > -- > 2.17.1 >