From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 54303 invoked by alias); 8 Oct 2018 14:51:37 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 54290 invoked by uid 89); 8 Oct 2018 14:51:36 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.9 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=day X-HELO: rock.gnat.com Received: from rock.gnat.com (HELO rock.gnat.com) (205.232.38.15) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 08 Oct 2018 14:51:35 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by filtered-rock.gnat.com (Postfix) with ESMTP id 68AE856034; Mon, 8 Oct 2018 10:51:34 -0400 (EDT) Received: from rock.gnat.com ([127.0.0.1]) by localhost (rock.gnat.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id u4wwuhfs08iF; Mon, 8 Oct 2018 10:51:34 -0400 (EDT) Received: from joel.gnat.com (localhost.localdomain [127.0.0.1]) by rock.gnat.com (Postfix) with ESMTP id 4CA2256030; Mon, 8 Oct 2018 10:51:34 -0400 (EDT) Received: by joel.gnat.com (Postfix, from userid 1000) id B94FE82C7F; Mon, 8 Oct 2018 10:51:32 -0400 (EDT) Date: Mon, 08 Oct 2018 14:51:00 -0000 From: Joel Brobecker To: Pedro Alves Cc: Paul Koning , Andrew Burgess , Craig Blackmore , gdb-patches@sourceware.org Subject: Re: [PATCH] RISC-V: enable have_nonsteppable_watchpoint by default Message-ID: <20181008145132.GB2993@adacore.com> References: <20180917103409.GJ5952@embecosm.com> <77978648-c391-0011-6c03-c7fd38429914@embecosm.com> <20181003223703.GA22933@adacore.com> <20181008095839.GC5952@embecosm.com> <4c4c1369-0f5c-549a-ed82-51563c5e6dd6@redhat.com> <20181008142533.GA2993@adacore.com> <5019D845-3AEB-4287-A8BD-D9F96F5755B7@comcast.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-SW-Source: 2018-10/txt/msg00178.txt.bz2 > > I think MIPS is one. The documentation is not entirely clear but > > that's what I remember from using it. > x86 is another. But my question is -- do we know of any RISC-V > implementation that triggers after the write, given that the spec > says it should trigger before the write. That was what I meant as well; I agree with Pedro that we don't really need to do anything fancy if: - the spec's recommendation is to trigger before the write - and we don't know of any system that decided to go against the recommendation. The day we discover a system that does in fact go against the recommendation, we can simply deal with it then and decide what the best course of action is. -- Joel