From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 97378 invoked by alias); 28 Sep 2018 09:44:02 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 97362 invoked by uid 89); 28 Sep 2018 09:44:01 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-3.2 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Envelope-From:sk:andrew., H*RU:209.85.221.66, Hx-spam-relays-external:209.85.221.66 X-HELO: mail-wr1-f66.google.com Received: from mail-wr1-f66.google.com (HELO mail-wr1-f66.google.com) (209.85.221.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 28 Sep 2018 09:43:59 +0000 Received: by mail-wr1-f66.google.com with SMTP id u12-v6so5654510wrr.4 for ; Fri, 28 Sep 2018 02:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=6CDrre/fJiafDbAfftHufvJxupuNqhedSqsHQ1UV9BM=; b=dmyzxYtH2flICNPt05nyXbHy6/sAPvsF1YUOjlVOIWbp0GcR4ZnZKYDO4t8JOJUArZ c2bl1GShB8HlZX9jXCGPLCekvQZtDsPlBuk8p7KIhF31hYnVK5BIBIGIDyCuyq9GwkzS TSxMYHzeyFvRxAmhWJl3IcsWVVb6NvvAdzxepWO8wwzJEGZyxT7IJ6hB7Tv6Nnn1VRlx sojGNpUR3QPsv9lxiFNWXMCGZ5SGUzaKO1wnUkGzsSp+ZUPN/TAjnIRX6LBLWxB43ODq XXy44bdICDhdGOPqqfmH3E8xynW8rcq5SupgHOir4ZfEjIQvHnTDABQToFWUG88USB/D kZxw== Return-Path: Received: from localhost (host81-154-73-63.range81-154.btcentralplus.com. [81.154.73.63]) by smtp.gmail.com with ESMTPSA id v6-v6sm4267580wro.66.2018.09.28.02.43.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 28 Sep 2018 02:43:56 -0700 (PDT) Date: Fri, 28 Sep 2018 09:44:00 -0000 From: Andrew Burgess To: Jim Wilson Cc: John Baldwin , gdb-patches@sourceware.org, Palmer Dabbelt Subject: Re: [PATCH 2/4] Fall back to a default value of 0 for the MISA register. Message-ID: <20180928094355.GS5952@embecosm.com> References: <20180919231950.22634-1-jhb@FreeBSD.org> <20180919231950.22634-3-jhb@FreeBSD.org> <0081bdf8-04cb-f6b7-d80a-d9a878d0a3ab@FreeBSD.org> <20180920215146.GW5952@embecosm.com> <4e2b6d40-dc15-6caa-8520-90289ce972da@FreeBSD.org> <20180921092721.GY5952@embecosm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Fortune: Stay away from flying saucers today. X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] User-Agent: Mutt/1.9.2 (2017-12-15) X-IsSubscribed: yes X-SW-Source: 2018-09/txt/msg00890.txt.bz2 * Jim Wilson [2018-09-21 10:25:47 -0700]: > On Fri, Sep 21, 2018 at 2:27 AM Andrew Burgess > wrote: > > Jim: Given that we agree that targets should definitely provide a > > value for misa, at a minimum just returning the constant 0. But, > > given that GDB already defaults to 0 in some cases anyway. And the > > spec is quite clear that 0 is the right default value in the absence > > of anything better, would you be OK with a patch that does return a > > default of 0? > > The patch to decode an instruction to decide whether to use a > compressed breakpoint or not solves my main problem. There is also > the issue of finding FP register size, but since we only support > rv64gc at the moment, it isn't a serious problem. I regularly test embeded RiscV against: rv32im rv32imc rv32imf rv32imfc rv64im rv64imc rv64imfd rv64imfdc with the last one of those being closes to rv64gc. The pass rate is broadly the same against all of these targets, so right now I consider these equally supported for baremetal. I understand Linux support might be different. Thanks, Andrew > Also, I think the > linker kernel may already be passing FP info via auxvec/hwcap, so I > think we already have an alternate solution for that which just needs > to be implemented. I haven't looked at that yet. So yes, I think it > is OK to start defaulting misa to 0. > > FYI I have a qemu patch, which I may someday finish, that adds XML > register support to the RISC-V qemu system-mode port, which allows > qemu to provide a correct value of misa. We know that misa accesses > already work with embedded targets via OpenOCD. So it is just linux > and freebsd that need to worry about misa. > > The qemu patch is here, though it looks like github is confused by > rebasing and the patch isn't readable anymore. > https://github.com/riscv/riscv-qemu/pull/160 > I'll have to figure out how to fix that. > > Jim