From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 98734 invoked by alias); 23 Aug 2017 06:29:02 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 98606 invoked by uid 89); 23 Aug 2017 06:28:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-6.4 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy=squashed, gavin, Gavin, Cleaned X-HELO: mail-pf0-f194.google.com Received: from mail-pf0-f194.google.com (HELO mail-pf0-f194.google.com) (209.85.192.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Aug 2017 06:28:52 +0000 Received: by mail-pf0-f194.google.com with SMTP id x137so775552pfd.0 for ; Tue, 22 Aug 2017 23:28:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=+CDTLTjwaWmIgFNL8RveWR4W9ceeWinnLd6FzJD3rvM=; b=YeU4pBKk91aSdPVj//60g2wRjb9CHty+SCxr2WrekUoKMtosznLnqHm1dvPU8lzd5H 9qyZPLspPPXFMdC4IApodb7iGCV6AVUYtPqcgBXUOYwTch9wrxY+8kkzKg8OWryjnQ6X DRrq7bISK4GOkzk49hVxK5dfVXCslmYq5p/QPJM1OqJp7Ukq5IgljfgGO0SQzQgpMvyF +mOr6WeTet5lb59NYjwqxd7WA+6eu1KO4xsrVab7oS02Dya/QRhAaBh83KQY8funt0X9 o5QFR5p6P54UKMsgkAL+Rh6WG/5OCcmidfOFZWLrT2ZYwnUyhbEl/AEeosuHsUmNc3G5 xn4g== X-Gm-Message-State: AHYfb5hBToImqdOybYM7bSX7b9orLmqQ2qV1e1OlYBxF4C7O9G/VsOEM kcYTRcxa6DJ41eQEUB2UCA== X-Received: by 10.84.218.3 with SMTP id q3mr1831088pli.282.1503469730278; Tue, 22 Aug 2017 23:28:50 -0700 (PDT) Received: from localhost (g28.222-224-182.ppp.wakwak.ne.jp. [222.224.182.28]) by smtp.gmail.com with ESMTPSA id 10sm1394654pfs.131.2017.08.22.23.28.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 23:28:49 -0700 (PDT) Date: Wed, 23 Aug 2017 06:29:00 -0000 From: Stafford Horne To: GDB patches Cc: Openrisc , Mike Frysinger , palves@redhat.com, dje@google.com, simon.marchi@ericsson.com, yao.qi@arm.com, eliz@gnu.org Subject: Re: [PATCH v4 0/5] sim port for OpenRISC Message-ID: <20170823062847.GB2587@lianli.shorne-pla.net> References: <20170613101549.GG6190@lianli.shorne-pla.net> <20170810132212.GC3031@lianli.shorne-pla.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170810132212.GC3031@lianli.shorne-pla.net> User-Agent: Mutt/1.8.3 (2017-05-23) X-IsSubscribed: yes X-SW-Source: 2017-08/txt/msg00431.txt.bz2 Hello Global Maintainers, Its been about a week since I sent the last ping Mike. It looks like he hasnt been active on the list since April. This is my patch series for the OpenRISC sim implementation needed to test and verify gdb. If possible I would like to have it reviewed so I commit this and gdb to upstream. At the moment it appears Mike may not be about to continue with the review. If someone knows more details please let us know. -Stafford On Thu, Aug 10, 2017 at 10:22:12PM +0900, Stafford Horne wrote: > Hello Again, > > Would anyone be willing to review these sim changes? Last reviewr was > Mike, please let me know. > > On Tue, Jun 13, 2017 at 07:15:49PM +0900, Stafford Horne wrote: > > Hi Mike, > > > > Sorry to bother you, > > Did you have a chance to look at this? > > > > -Stafford > > > > On Mon, May 29, 2017 at 11:47:25PM +0900, Stafford Horne wrote: > > > Hello, > > > > > > Please find attached the sim patches that allow to get a basic OpenRISC > > > system running. This was used to verify the OpenRISC gdb port. > > > > > > The main author is Peter Gavin who should have his FSF copyright in place. > > > > > > Request for comments on: > > > - Openrisc supports a l.rem instruction which has been implemented here > > > using the remainder() function from libmath. It seems no other > > > functions use libmath now, I hope this is ok. > > > > > > Sim dejagnu tests were added specifically for openrisc and used to test > > > this. Please see the details of running the testsuite for sim below: > > > > > > === sim Summary === > > > > > > # of expected passes 17 > > > /home/shorne/work/openrisc/build-gdb/sim/or1k/run 0.5 > > > > > > -Stafford > > > > > > -- > > > > > > Changes since v3 > > > * Cleaned up indentation and style of sim testsuite > > > * Cleaned up TODOs in testsuite > > > * Implemented range exception > > > > > > Changes since v2 > > > * Removed 64-bit implementation (reduced files) > > > * Removed cgen suffix patch > > > * Removed different builds for linux > > > * Removed unused macros > > > * Fixed gnu style issues pointed out by Mike > > > * Fixed copyrights (not Cygnus, added to each file) > > > > > > Changes since v1 > > > * Squashed sim patches into single sim patch > > > * Put Generated files in separate patch > > > * I have my sim/gdb copyright assignment complete > > > > > > -- > > > > > > Peter Gavin (3): > > > sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd]) > > > sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u]) > > > sim: testsuite: add testsuite for or1k sim > > > > > > Stafford Horne (2): > > > sim: or1k: add or1k target to sim > > > sim: or1k: Add generated files. > > > > > > sim/common/cgen-accfp.c | 40 + > > > sim/common/cgen-fpu.h | 4 + > > > sim/common/cgen-ops.h | 18 + > > > sim/common/sim-fpu.c | 63 + > > > sim/common/sim-fpu.h | 3 + > > > sim/configure | 9 + > > > sim/configure.tgt | 4 + > > > sim/or1k/Makefile.in | 142 + > > > sim/or1k/aclocal.m4 | 119 + > > > sim/or1k/arch.c | 38 + > > > sim/or1k/arch.h | 50 + > > > sim/or1k/config.in | 248 + > > > sim/or1k/configure | 16043 +++++++++++++++++++++++ > > > sim/or1k/configure.ac | 17 + > > > sim/or1k/cpu.c | 10181 ++++++++++++++ > > > sim/or1k/cpu.h | 5024 +++++++ > > > sim/or1k/cpuall.h | 66 + > > > sim/or1k/decode.c | 2559 ++++ > > > sim/or1k/decode.h | 94 + > > > sim/or1k/eng.h | 34 + > > > sim/or1k/mloop.in | 242 + > > > sim/or1k/model.c | 3809 ++++++ > > > sim/or1k/or1k-sim.h | 94 + > > > sim/or1k/or1k.c | 328 + > > > sim/or1k/sem-switch.c | 2748 ++++ > > > sim/or1k/sem.c | 2953 +++++ > > > sim/or1k/sim-if.c | 270 + > > > sim/or1k/sim-main.h | 80 + > > > sim/or1k/traps.c | 209 + > > > sim/testsuite/configure | 4 + > > > sim/testsuite/sim/or1k/add.S | 606 + > > > sim/testsuite/sim/or1k/alltests.exp | 34 + > > > sim/testsuite/sim/or1k/and.S | 198 + > > > sim/testsuite/sim/or1k/basic.S | 522 + > > > sim/testsuite/sim/or1k/div.S | 290 + > > > sim/testsuite/sim/or1k/ext.S | 236 + > > > sim/testsuite/sim/or1k/find.S | 100 + > > > sim/testsuite/sim/or1k/flag.S | 378 + > > > sim/testsuite/sim/or1k/jump.S | 104 + > > > sim/testsuite/sim/or1k/load.S | 358 + > > > sim/testsuite/sim/or1k/mac.S | 778 ++ > > > sim/testsuite/sim/or1k/mfspr.S | 171 + > > > sim/testsuite/sim/or1k/mul.S | 573 + > > > sim/testsuite/sim/or1k/or.S | 199 + > > > sim/testsuite/sim/or1k/or1k-asm-test-env.h | 59 + > > > sim/testsuite/sim/or1k/or1k-asm-test-helpers.h | 121 + > > > sim/testsuite/sim/or1k/or1k-asm-test.h | 225 + > > > sim/testsuite/sim/or1k/or1k-asm.h | 37 + > > > sim/testsuite/sim/or1k/or1k-test.ld | 75 + > > > sim/testsuite/sim/or1k/ror.S | 159 + > > > sim/testsuite/sim/or1k/shift.S | 541 + > > > sim/testsuite/sim/or1k/spr-defs.h | 120 + > > > sim/testsuite/sim/or1k/sub.S | 201 + > > > sim/testsuite/sim/or1k/xor.S | 200 + > > > 54 files changed, 51778 insertions(+) > > > create mode 100644 sim/or1k/Makefile.in > > > create mode 100644 sim/or1k/aclocal.m4 > > > create mode 100644 sim/or1k/arch.c > > > create mode 100644 sim/or1k/arch.h > > > create mode 100644 sim/or1k/config.in > > > create mode 100755 sim/or1k/configure > > > create mode 100644 sim/or1k/configure.ac > > > create mode 100644 sim/or1k/cpu.c > > > create mode 100644 sim/or1k/cpu.h > > > create mode 100644 sim/or1k/cpuall.h > > > create mode 100644 sim/or1k/decode.c > > > create mode 100644 sim/or1k/decode.h > > > create mode 100644 sim/or1k/eng.h > > > create mode 100644 sim/or1k/mloop.in > > > create mode 100644 sim/or1k/model.c > > > create mode 100644 sim/or1k/or1k-sim.h > > > create mode 100644 sim/or1k/or1k.c > > > create mode 100644 sim/or1k/sem-switch.c > > > create mode 100644 sim/or1k/sem.c > > > create mode 100644 sim/or1k/sim-if.c > > > create mode 100644 sim/or1k/sim-main.h > > > create mode 100644 sim/or1k/traps.c > > > create mode 100644 sim/testsuite/sim/or1k/add.S > > > create mode 100644 sim/testsuite/sim/or1k/alltests.exp > > > create mode 100644 sim/testsuite/sim/or1k/and.S > > > create mode 100644 sim/testsuite/sim/or1k/basic.S > > > create mode 100644 sim/testsuite/sim/or1k/div.S > > > create mode 100644 sim/testsuite/sim/or1k/ext.S > > > create mode 100644 sim/testsuite/sim/or1k/find.S > > > create mode 100644 sim/testsuite/sim/or1k/flag.S > > > create mode 100644 sim/testsuite/sim/or1k/jump.S > > > create mode 100644 sim/testsuite/sim/or1k/load.S > > > create mode 100644 sim/testsuite/sim/or1k/mac.S > > > create mode 100644 sim/testsuite/sim/or1k/mfspr.S > > > create mode 100644 sim/testsuite/sim/or1k/mul.S > > > create mode 100644 sim/testsuite/sim/or1k/or.S > > > create mode 100644 sim/testsuite/sim/or1k/or1k-asm-test-env.h > > > create mode 100644 sim/testsuite/sim/or1k/or1k-asm-test-helpers.h > > > create mode 100644 sim/testsuite/sim/or1k/or1k-asm-test.h > > > create mode 100644 sim/testsuite/sim/or1k/or1k-asm.h > > > create mode 100644 sim/testsuite/sim/or1k/or1k-test.ld > > > create mode 100644 sim/testsuite/sim/or1k/ror.S > > > create mode 100644 sim/testsuite/sim/or1k/shift.S > > > create mode 100644 sim/testsuite/sim/or1k/spr-defs.h > > > create mode 100644 sim/testsuite/sim/or1k/sub.S > > > create mode 100644 sim/testsuite/sim/or1k/xor.S > > > > > > -- > > > 2.9.4 > > >