From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 111367 invoked by alias); 16 May 2017 11:18:37 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 110902 invoked by uid 89); 16 May 2017 11:18:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-6.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_1,RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_SPAM,SPF_PASS autolearn=ham version=3.3.2 spammy=Embedded, advised, HContent-Transfer-Encoding:8bit X-HELO: mail-pg0-f54.google.com Received: from mail-pg0-f54.google.com (HELO mail-pg0-f54.google.com) (74.125.83.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 May 2017 11:18:35 +0000 Received: by mail-pg0-f54.google.com with SMTP id u187so74892655pgb.0 for ; Tue, 16 May 2017 04:18:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=wWPzwv4EwyGQIxQ9ojH5vv8XwRKCp7vG9G4pMxuHrMc=; b=MJQq2Zyu2ckt+qaphH2YH2JKyGrnt93UBBmjI0EEzh5yil/m+F6DNE6sRpH4Hi1uDz /ynLwlLh/qRK+YUlr6knWxLTTrss/7MrCsObnbI9IQSGDjsiNEX3P00r6LQcQgLyqb6Q eNeU0yxjxBtI/B69DtKuHlfMJ5y92hfxGF1CuJ63Mji/+CJG124s5lEmPGbMp29J/wbt DfnR4DFw/tZTSAdIJNTk9LDuZrWT3wyDN8Pf70NvI16FCHUjrBDKF629iQe7+NPMvf3U vzm6vLxrmUR0gA75f79EupHb54pbYILyObS/0Tw2AZRfIfPqjkD+jpgRSn4moJwjhTV/ MEug== X-Gm-Message-State: AODbwcAQGkLTG0hvh97F/DtEhl1AMekS3idWKLQj6Rl/l/zqY8cFF0Y8 6SqVcMqnwUrIBqtG X-Received: by 10.84.217.141 with SMTP id p13mr14802068pli.59.1494933516688; Tue, 16 May 2017 04:18:36 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id k23sm23592338pgn.11.2017.05.16.04.18.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 May 2017 04:18:36 -0700 (PDT) Date: Tue, 16 May 2017 11:18:00 -0000 From: Stafford Horne To: Yao Qi Cc: GDB patches , Openrisc , Franck Jullien Subject: Re: [PATCH v6 2/5] gdb: Add OpenRISC or1k and or1knd target support Message-ID: <20170516111828.GD2440@lianli.shorne-pla.net> References: <864lx38h2i.fsf@gmail.com> <20170502155305.GI2724@lianli.shorne-pla.net> <86shket8tx.fsf@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <86shket8tx.fsf@gmail.com> User-Agent: Mutt/1.8.0 (2017-02-23) X-IsSubscribed: yes X-SW-Source: 2017-05/txt/msg00338.txt.bz2 On Tue, May 09, 2017 at 03:15:38PM +0100, Yao Qi wrote: > Stafford Horne writes: > > > I understand this is nothing new, but this tells to the users some extra > > details about using target remote for OpenRISC (example which platforms > > support it). Also, this is consistent with some other targets like > > Microblaze. > > > > All the targets listed in "Embedded Processors" do have "target > remote". We don't have to document it for every one. IMO, we need to > remove "target remote" from Microblaze part too. Sure I will remove. Also I am adding 'set debug or1k' and 'show debug or1k'. > >> > + > >> > +@kindex target sim > >> > +@item target sim > >> > + > >> > +Runs the builtin CPU simulator which can run very basic > >> > +programs but does not support most hardware functions like MMU. > >> > +For more complex use cases the user is advised to run an external > >> > +target, and connect using @samp{target remote}. > >> > + > >> > +Example: @code{target sim} > >> > + > >> > +@end table > >> > + > >> > @node PowerPC Embedded > >> > @subsection PowerPC Embedded > >> > > >> > @@ -41088,6 +41131,7 @@ registers using the capitalization used in > >> > the description. > >> > * M68K Features:: > >> > * NDS32 Features:: > >> > * Nios II Features:: > >> > +* OpenRISC 1000 Features:: > >> > * PowerPC Features:: > >> > * S/390 and System z Features:: > >> > * Sparc Features:: > >> > @@ -41374,6 +41418,32 @@ targets. It should contain the 32 core > >> > registers (@samp{zero}, > >> > @samp{pc}, and the 16 control registers (@samp{status} through > >> > @samp{mpuacc}). > >> > > >> > +@node OpenRISC 1000 Features > >> > +@subsection Openrisc 1000 Features > >> > +@cindex target descriptions, OpenRISC 1000 features > >> > + > >> > +The @samp{org.gnu.gdb.or1k.group0} feature is required for OpenRISC 1000 > >> > +targets. It should contain the 32 general purpose registers (@samp{r0} > >> > +through @samp{r31}), @samp{ppc}, @samp{npc} and @samp{sr}. > >> > + > >> > +Along with the default reggroups like @samp{system} and @samp{general} > >> > +provided by @value{GDBN}, OpenRISC targets can use the following reggroups > >> > +to group their many registers: > >> > + > >> > +@smallexample > >> > + Group Type > >> > + immu user > >> > + dmmu user > >> > + icache user > >> > + dcache user > >> > + pic user > >> > + timer user > >> > + power user > >> > + perf user > >> > + mac user > >> > + debug user > >> > +@end smallexample > >> > + > >> > >> Why do you need to document the reggroups? > > > > These register groups can be used by the target description features. If > > not documented one would have to look into the code. In general arbitrary > > groups are not allowed by features. This is also related to patch 1/5. > > "maintenance print reggroups" can tell the reggroups, so don't need to > document them. Sure, I will remove. > -- > Yao (齐尧)