From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 82942 invoked by alias); 2 May 2017 15:53:10 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 82924 invoked by uid 89); 2 May 2017 15:53:09 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-6.3 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,GIT_PATCH_1,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=Stafford X-HELO: mail-pf0-f171.google.com Received: from mail-pf0-f171.google.com (HELO mail-pf0-f171.google.com) (209.85.192.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 02 May 2017 15:53:07 +0000 Received: by mail-pf0-f171.google.com with SMTP id e64so53623908pfd.1 for ; Tue, 02 May 2017 08:53:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=taJxKdIpcETM+t8l2hfqK+3kZORTkKAG0i3diWibYng=; b=KaClvYrOrQ2xvKE5rpxomgo6I3qo3zKvOG/6HT4RjBp7BdmMoeWG6uIr3W9iuE9jbl ABAXPjycpqxPU8CfMki7KRHZJKTJyNNNlB1m4rYnNEZV5imeusqoiJJcU9SdAZ0AT1Oq MM147bUwc9i4P2hgut66nbINiZTYN2vxqyyYXgjX5FO6IXPMknkzxiN0HgcghL44Q4f0 IiHGt1SzeEsBRsKjgX1n/boIOvbXFXvLm1lyfBeI8mS54KGED/QYkYZ4pBTBaiokWUIh 8JmrWaB4RZd1/SP/QqKQzgPpfbrtXrgffjpPA+FMp1EbAGwJC4rDW8Ztww8TQh4fcfS7 rjpQ== X-Gm-Message-State: AN3rC/6lZuhAom6PKbt50zqYMFcwzPQLcakw2mpyzRkDKT60kg1zdwUt 8wpwoQIyiqGFHaZn X-Received: by 10.84.177.164 with SMTP id x33mr42015763plb.147.1493740388710; Tue, 02 May 2017 08:53:08 -0700 (PDT) Received: from localhost (z209.124-44-183.ppp.wakwak.ne.jp. [124.44.183.209]) by smtp.gmail.com with ESMTPSA id 20sm41607090pfq.42.2017.05.02.08.53.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 02 May 2017 08:53:08 -0700 (PDT) Date: Tue, 02 May 2017 15:53:00 -0000 From: Stafford Horne To: Yao Qi Cc: GDB patches , Openrisc , Franck Jullien Subject: Re: [PATCH v6 2/5] gdb: Add OpenRISC or1k and or1knd target support Message-ID: <20170502155305.GI2724@lianli.shorne-pla.net> References: <864lx38h2i.fsf@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <864lx38h2i.fsf@gmail.com> User-Agent: Mutt/1.8.0 (2017-02-23) X-IsSubscribed: yes X-SW-Source: 2017-05/txt/msg00015.txt.bz2 On Tue, May 02, 2017 at 03:32:53PM +0100, Yao Qi wrote: > Stafford Horne writes: > > > +@kindex target remote > > +@item target remote > > + > > +Connect to a remote OpenRISC 1000 target. This is supported by > > +@dfn{Or1ksim}, the OpenRISC 1000 architectural simulator as well as QEMU, > > +Verilator and Icarus Verilog simulators. @dfn{Remote serial protocol} > > +servers, such as OpenOCD, are also available to drive various hardware > > +implementations via JTAG. > > + > > +Example: @code{target remote :51000} > > Do we need to document "target remote"? which is not specific to any > particular configurations. I understand this is nothing new, but this tells to the users some extra details about using target remote for OpenRISC (example which platforms support it). Also, this is consistent with some other targets like Microblaze. > > + > > +@kindex target sim > > +@item target sim > > + > > +Runs the builtin CPU simulator which can run very basic > > +programs but does not support most hardware functions like MMU. > > +For more complex use cases the user is advised to run an external > > +target, and connect using @samp{target remote}. > > + > > +Example: @code{target sim} > > + > > +@end table > > + > > @node PowerPC Embedded > > @subsection PowerPC Embedded > > > > @@ -41088,6 +41131,7 @@ registers using the capitalization used in the description. > > * M68K Features:: > > * NDS32 Features:: > > * Nios II Features:: > > +* OpenRISC 1000 Features:: > > * PowerPC Features:: > > * S/390 and System z Features:: > > * Sparc Features:: > > @@ -41374,6 +41418,32 @@ targets. It should contain the 32 core registers (@samp{zero}, > > @samp{pc}, and the 16 control registers (@samp{status} through > > @samp{mpuacc}). > > > > +@node OpenRISC 1000 Features > > +@subsection Openrisc 1000 Features > > +@cindex target descriptions, OpenRISC 1000 features > > + > > +The @samp{org.gnu.gdb.or1k.group0} feature is required for OpenRISC 1000 > > +targets. It should contain the 32 general purpose registers (@samp{r0} > > +through @samp{r31}), @samp{ppc}, @samp{npc} and @samp{sr}. > > + > > +Along with the default reggroups like @samp{system} and @samp{general} > > +provided by @value{GDBN}, OpenRISC targets can use the following reggroups > > +to group their many registers: > > + > > +@smallexample > > + Group Type > > + immu user > > + dmmu user > > + icache user > > + dcache user > > + pic user > > + timer user > > + power user > > + perf user > > + mac user > > + debug user > > +@end smallexample > > + > > Why do you need to document the reggroups? These register groups can be used by the target description features. If not documented one would have to look into the code. In general arbitrary groups are not allowed by features. This is also related to patch 1/5. > > + > > +extern initialize_file_ftype _initialize_or1k_tdep; /* -Wmissing-prototypes */ > > + > > This is no longer needed, because GDB is moved to C++. > > Otherwise, the code is good to me. > > -- > Yao (齐尧)