From: Mike Frysinger <vapier@gentoo.org>
To: Stafford Horne <shorne@gmail.com>
Cc: gdb-patches@sourceware.org, openrisc@lists.librecores.org
Subject: Re: [PATCH v2 4/6] sim: or1k: add or1k target to sim
Date: Wed, 15 Feb 2017 15:42:00 -0000 [thread overview]
Message-ID: <20170215154207.GN28432@vapier> (raw)
In-Reply-To: <20170215132222.GA1603@lianli.shorne-pla.net>
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On 15 Feb 2017 22:24, Stafford Horne wrote:
> Before, we get started I just want to point out that some of these
> issues seem pretty obvious, but this code had been sitting in the
> openrisc source repo's for some time. I believe it was done on contract
> by the people mentioned in the cover letter, who may have worked at
> Cygnus.
i suspected it's an old port because it looks like it was copied from
another sim port, but before a lot of cleanups were done. there has
been a bunch of fixups across the codebase to try and make things easy
for new ports.
-mike
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next prev parent reply other threads:[~2017-02-15 15:42 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-21 3:04 [PATCH v2 0/6] sim: Port for OpenRISC Stafford Horne
2017-01-21 3:04 ` [PATCH v2 3/6] sim: cgen: allow suffix on generated arch.[ch] and cpuall.h Stafford Horne
2017-01-21 3:04 ` [PATCH v2 1/6] sim: cgen: add rem (remainder) function (needed for OR1K lf.rem.[sd]) Stafford Horne
2017-01-21 3:04 ` [PATCH v2 4/6] sim: or1k: add or1k target to sim Stafford Horne
2017-02-14 18:52 ` Mike Frysinger
2017-02-15 13:25 ` Stafford Horne
2017-02-15 15:42 ` Mike Frysinger [this message]
2017-02-28 11:39 ` Stafford Horne
2017-01-21 3:04 ` [PATCH v2 2/6] sim: cgen: add mul-o1flag, mul-o2flag RTL functions to CGEN Stafford Horne
2017-01-21 3:05 ` [PATCH v2 6/6] sim: testsuite: add testsuite for or1k sim Stafford Horne
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