[PATCH v2 2/2] Add testsuite for the PRU simulator port

Dimitar Dimitrov
2016-12-27T21:26:14Z

2016-12-26 Dimitar Dimitrov <dimitar@dinux.eu>

sim/test

* configure: Regenerate.
* pru: New directory.

Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
---
sim/testsuite/configure | 3 ++
sim/testsuite/sim/pru/ChangeLog | 14 +++++++
sim/testsuite/sim/pru/add.s | 22 ++++++++++
sim/testsuite/sim/pru/allinsn.exp | 15 +++++++
sim/testsuite/sim/pru/dmem-zero-pass.s | 11 +++++
sim/testsuite/sim/pru/dmem-zero-trap.s | 14 +++++++
sim/testsuite/sim/pru/dram.s | 54 +++++++++++++++++++++++++
sim/testsuite/sim/pru/jmp.s | 22 ++++++++++
sim/testsuite/sim/pru/loop-imm.s | 25 ++++++++++++
sim/testsuite/sim/pru/loop-reg.s | 26 ++++++++++++
sim/testsuite/sim/pru/subreg.s | 22 ++++++++++
sim/testsuite/sim/pru/testutils.inc | 73 ++++++++++++++++++++++++++++++++++
12 files changed, 301 insertions(+)
create mode 100644 sim/testsuite/sim/pru/ChangeLog
create mode 100644 sim/testsuite/sim/pru/add.s
create mode 100644 sim/testsuite/sim/pru/allinsn.exp
create mode 100644 sim/testsuite/sim/pru/dmem-zero-pass.s
create mode 100644 sim/testsuite/sim/pru/dmem-zero-trap.s
create mode 100644 sim/testsuite/sim/pru/dram.s
create mode 100644 sim/testsuite/sim/pru/jmp.s
create mode 100644 sim/testsuite/sim/pru/loop-imm.s
create mode 100644 sim/testsuite/sim/pru/loop-reg.s
create mode 100644 sim/testsuite/sim/pru/subreg.s
create mode 100644 sim/testsuite/sim/pru/testutils.inc

diff --git a/sim/testsuite/configure b/sim/testsuite/configure
index bbc3bea48d..6565debbfc 100755
--- a/sim/testsuite/configure
+++ b/sim/testsuite/configure
@@ -1906,6 +1906,9 @@ case "${target}" in
powerpc*-*-*)
sim_arch=ppc
;;
+ pru*-*-*)
+ sim_arch=pru
+ ;;
ft32-*-*)
sim_arch=ft32
;;
diff --git a/sim/testsuite/sim/pru/ChangeLog b/sim/testsuite/sim/pru/ChangeLog
new file mode 100644
index 0000000000..7a141ed47e
--- /dev/null
+++ b/sim/testsuite/sim/pru/ChangeLog
@@ -0,0 +1,14 @@
+2016-12-26 Dimitar Dimitrov <dimitar@dinux.eu>
+
+ * ChangeLog: New file.
+ * add.s: New test.
+ * allinsn.exp: New file.
+ * dmem-zero-pass.s: New test.
+ * dmem-zero-trap.s: New test.
+ * dram.s: New test.
+ * jmp.s: New test.
+ * loop-imm.s: New test.
+ * loop-reg.s: New test.
+ * subreg.s: New test.
+ * testutils.inc: New file.
+
diff --git a/sim/testsuite/sim/pru/add.s b/sim/testsuite/sim/pru/add.s
new file mode 100644
index 0000000000..10bdd9a8ef
--- /dev/null
+++ b/sim/testsuite/sim/pru/add.s
@@ -0,0 +1,22 @@
+# check that basic add insn works.
+# mach: pru
+
+.include "testutils.inc"
+
+ start
+
+ ldi r4, 10
+ add r4, r4, 23
+ qbne 2f, r4, 33
+
+ qblt 2f, r4, 33
+
+ qbgt 2f, r4, 33
+
+ jmp 1f
+
+ fail
+
+1:
+ pass
+2: fail
diff --git a/sim/testsuite/sim/pru/allinsn.exp b/sim/testsuite/sim/pru/allinsn.exp
new file mode 100644
index 0000000000..6e50710224
--- /dev/null
+++ b/sim/testsuite/sim/pru/allinsn.exp
@@ -0,0 +1,15 @@
+# PRU simulator testsuite
+
+if [istarget pru-*] {
+ # all machines
+ set all_machs "pru"
+
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
+ # If we're only testing specific files and this isn't one of them,
+ # skip it.
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+ run_sim_test $src $all_machs
+ }
+}
diff --git a/sim/testsuite/sim/pru/dmem-zero-pass.s b/sim/testsuite/sim/pru/dmem-zero-pass.s
new file mode 100644
index 0000000000..3cdc715d35
--- /dev/null
+++ b/sim/testsuite/sim/pru/dmem-zero-pass.s
@@ -0,0 +1,11 @@
+# check that DMEM zero address access works by default.
+# mach: pru
+
+.include "testutils.inc"
+
+ start
+
+ ldi r1, 0
+ lbbo &r2, r1, 0, 4
+
+ pass
diff --git a/sim/testsuite/sim/pru/dmem-zero-trap.s b/sim/testsuite/sim/pru/dmem-zero-trap.s
new file mode 100644
index 0000000000..55d8a22505
--- /dev/null
+++ b/sim/testsuite/sim/pru/dmem-zero-trap.s
@@ -0,0 +1,14 @@
+# check that DMEM zero address access can be trapped.
+# mach: pru
+# sim: --error-null-deref
+# xerror:
+# output: core: 4 byte read to unmapped address 0x0 at *\n
+
+.include "testutils.inc"
+
+ start
+
+ ldi r1, 0
+ lbbo &r2, r1, 0, 4
+
+ pass
diff --git a/sim/testsuite/sim/pru/dram.s b/sim/testsuite/sim/pru/dram.s
new file mode 100644
index 0000000000..2a998b566c
--- /dev/null
+++ b/sim/testsuite/sim/pru/dram.s
@@ -0,0 +1,54 @@
+# check that DRAM memory access works.
+# mach: pru
+
+.include "testutils.inc"
+
+ start
+
+ fill r20, 16
+ ldi r10, 0
+ not r10, r10
+ qbne F, r20, r10
+ qbne F, r21, r10
+ qbne F, r22, r10
+ qbne F, r23, r10
+
+ zero r20, 16
+ qbne F, r20, 0
+ qbne F, r21, 0
+ qbne F, r22, 0
+ qbne F, r23, 0
+
+ ldi r0, testarray
+ lbbo &r20, r0, 0, 7
+ qbne F, r20.b0, 0x01
+ qbne F, r20.b1, 0x23
+ qbne F, r20.b2, 0x45
+ qbne F, r20.b3, 0x67
+ qbne F, r21.b0, 0x89
+ qbne F, r21.b1, 0xab
+ qbne F, r21.b2, 0xcd
+ qbne F, r21.b3, 0x00 ; Should not have been loaded!
+ qbne F, r22, 0
+ qbne F, r23, 0
+
+ ldi r1, 0x11
+ sbbo &r1, r0, 9, 1
+ ldi r1, 0x11
+ sbbo &r1, r0, 12, 4
+
+ lbbo &r20, r0, 0, 16
+ qbne F, r21.b3, 0xef
+ qbne F, r22.b0, 0xff
+ qbne F, r22.b1, 0x11
+ qbne F, r22.b2, 0xff
+ qbne F, r22.b3, 0xff
+ qbne F, r23, 0x11
+
+ pass
+F: fail
+
+ .data
+testarray:
+ .byte 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef
+ .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
diff --git a/sim/testsuite/sim/pru/jmp.s b/sim/testsuite/sim/pru/jmp.s
new file mode 100644
index 0000000000..d01d78f823
--- /dev/null
+++ b/sim/testsuite/sim/pru/jmp.s
@@ -0,0 +1,22 @@
+# check that basic add insn works.
+# mach: pru
+
+.include "testutils.inc"
+
+ start
+
+ ldi r10, 10
+ call func1
+ qbne F, r10, 11
+
+ ldi r0, %pmem(1f)
+ jmp r0
+ fail
+1:
+ pass
+F: fail
+
+
+func1:
+ add r10, r10, 1
+ ret
diff --git a/sim/testsuite/sim/pru/loop-imm.s b/sim/testsuite/sim/pru/loop-imm.s
new file mode 100644
index 0000000000..118219b54c
--- /dev/null
+++ b/sim/testsuite/sim/pru/loop-imm.s
@@ -0,0 +1,25 @@
+# check that loop insn works.
+# mach: pru
+
+.include "testutils.inc"
+
+ start
+
+ ldi r25, 0
+ ldi r26, 0
+ ldi r27, 0
+
+ add r27, r27, 1
+ loop 1f, 10
+ add r25, r25, 1
+ add r26, r26, 2
+1:
+ add r27, r27, 1
+
+ qbne F, r25, 10
+ qbne F, r26, 20
+ qbne F, r27, 2
+
+ pass
+
+F: fail
diff --git a/sim/testsuite/sim/pru/loop-reg.s b/sim/testsuite/sim/pru/loop-reg.s
new file mode 100644
index 0000000000..d4843e9415
--- /dev/null
+++ b/sim/testsuite/sim/pru/loop-reg.s
@@ -0,0 +1,26 @@
+# check that loop insn works.
+# mach: pru
+
+.include "testutils.inc"
+
+ start
+
+ ldi r25, 0
+ ldi r26, 0
+ ldi r27, 0
+ ldi r28, 10
+
+ add r27, r27, 1
+ loop 1f, r28
+ add r25, r25, 1
+ add r26, r26, 2
+1:
+ add r27, r27, 1
+
+ qbne F, r25, 10
+ qbne F, r26, 20
+ qbne F, r27, 2
+
+ pass
+
+F: fail
diff --git a/sim/testsuite/sim/pru/subreg.s b/sim/testsuite/sim/pru/subreg.s
new file mode 100644
index 0000000000..a100e411b2
--- /dev/null
+++ b/sim/testsuite/sim/pru/subreg.s
@@ -0,0 +1,22 @@
+# check that subregister addressing works.
+# mach: pru
+
+.include "testutils.inc"
+
+ start
+
+ ldi r0, 0x01ff
+ add r0, r0.b0, r0.b1
+ qbne F, r0.b0, 0x00
+ qbne F, r0.b1, 0x01
+ qbne F, r0.w2, 0x00
+
+ ldi r0, 0x01ff
+ add r0.b0, r0.b0, r0.b1
+ adc r0, r0.b1, r0.b3
+ qbne F, r0.b0, 0x02
+ qbne F, r0.b1, 0x00
+ qbne F, r0.w2, 0x00
+
+ pass
+F: fail
diff --git a/sim/testsuite/sim/pru/testutils.inc b/sim/testsuite/sim/pru/testutils.inc
new file mode 100644
index 0000000000..7a5029f90e
--- /dev/null
+++ b/sim/testsuite/sim/pru/testutils.inc
@@ -0,0 +1,73 @@
+# MACRO: start
+# All assembler tests should start with a call to "main_test"
+ .macro start
+ .text
+
+ .global _start
+_start:
+
+ # Skip over these inlined funcs.
+ jmp __main_test;
+
+ .global __pass
+ .type __pass, function
+__pass:
+ # Note - DRAM LMA and VMA are equal for PRU, so
+ # we can afford to pass DRAM pointer directly.
+ write 1, _passmsg, 5
+ exit 0
+
+ .global __fail
+ .type __fail, function
+__fail:
+ write 1, _failmsg, 5
+ exit 1
+
+ .data
+_passmsg:
+ .ascii "pass\n"
+
+_failmsg:
+ .ascii "fail\n"
+
+ .text
+ .global __main_test
+ .type __main_test, function
+__main_test:
+ .endm
+
+# MACRO: system_call
+# Make a libgloss system call
+ .macro system_call nr:req, arg1=0, arg2=0, arg3=0
+ ldi r1, \nr
+ ldi r14, \arg1
+ ldi r15, \arg2
+ ldi r16, \arg3
+ halt
+ .endm
+
+# MACRO: exit
+# Quit the current test
+ .macro exit rc:req
+ system_call 1, \rc
+ .endm
+
+# MACRO: pass
+# Write 'pass' to stdout via syscalls and quit;
+# meant for non-OS operating environments
+ .macro pass
+ jmp __pass;
+ .endm
+
+# MACRO: fail
+# Write 'fail' to stdout via syscalls and quit;
+# meant for non-OS operating environments
+ .macro fail
+ jmp __fail;
+ .endm
+
+# MACRO: write
+# Just like the write() C function; uses system calls
+ .macro write fd:req, str:req, len:req
+ system_call 5, \fd, \str, \len
+ .endm
--
2.11.0