On 18 Mar 2016 09:32, Nick Clifton wrote:
> +#define GET_VEC_ELEMENT(REG, ELEMENT, FIELD)	   \

is using all caps for arg names a normal style thing ?

> +  do						   \
> +    {						   \
> +      if (element > ARRAY_SIZE (cpu->fr[0].FIELD)) \

shouldn't this be ELEMENT ?  and be >= ?

> +#define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER)	\
> +  do						   		\
> +    {								\
> +      if (ELEMENT > ARRAY_SIZE (cpu->fr[0].FIELD))			\

>= ?
-mike