Re: [PATCH v4 03/13] sim/erc32: Switched emulated memory to host endian order.

Jiri Gaisler
2015-03-28T08:21:37Z

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On 28/03/15 08:41, Mike Frysinger wrote:
> On 23 Mar 2015 10:00, Jiri Gaisler wrote:
>> On 23/03/15 03:45, Mike Frysinger wrote:
>>> On 17 Mar 2015 22:02, Jiri Gaisler wrote:
>>>> --- a/sim/erc32/erc32.c
>>>> +++ b/sim/erc32/erc32.c
>>>> +#ifdef HOST_LITTLE_ENDIAN
>>>> + waddr ^= 3;
>>>> +#endif
>>>> + mem[waddr] = *data & 0x0ff;
>>>
>>> doesn't this assume the target is big endian ? this shows up a few times in
>>> the changes to this file.
>>
>> The target (SPARC) is always big endian, so I believe this is correct.
>
> wikipedia says:
> The endianness of the 32-bit SPARC V8 architecture is purely big-endian. The
> 64-bit SPARC V9 architecture uses big-endian instructions, but can access data
> in either big-endian or little-endian byte order, chosen either at the
> application instruction (load/store) level or at the memory page level (via an
> MMU setting). The latter is often used for accessing data from inherently
> little-endian devices, such as those on PCI buses.
>
> but i guess that'll need quite a bit of work to fix up ?

The sis simulator is strictly SPARC V8 (32-bit), so there is nothing to fix up really.
I have no plans to add V9 (64-bit) so staying big endian should be safe.

Jiri.

> -mike
>

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