Re: Breakage with: Commit: V850 SIM: Add support for e3v5 instructions

Nicholas Clifton
2015-02-27T09:49:16Z

[-- Attachment #1: Type: text/plain, Size: 1153 bytes --]

Hi Hans-Peter,

> Hi Nick. Deja-vu here, but this time sim. I'm a bit worried
> now: what is going wrong with my replies to your patches?

I don't know - I am just not seeing them. I have checked my junk logs
and they are not in there.

>> /tmp/hpautotest-sim/src/sim/v850/v850.igen:4177: warning: v850e3v5.63.16.0: C.vadd.h was not uniquely decoded
>> /tmp/hpautotest-sim/src/sim/v850/v850.igen:1538: warning: v850e3v5.63.16.0: IX.sasf decodes to the same entry

Sorry about that - I forgot to update the v850-dc file.

I am checking in the attached patch to fix this. (It also fixes all the
compile time warnings that I was seeing, so the v850 sim sources should
compile cleanly now).

Cheers
Nick

sim/v850/ChangeLog
2015-02-27 Nick Clifton <nickc@redhat.com>

* sim-main.h (reg64_t): New type.
(v850_regs): Add selID_sregs field.
(VR, SAT16, SAT32, ABS16, ABS32 ): New macros.
* v850-dc: Add fields for v850e3v5 instructions.
* v850.igen (cvtf.dl): Use correctly signed local value.
(cvtf.dw, cvtf.sw, trncf.dul, trncf.dl, trncf.sul, trncf.sw):
Likewise.
* interp.c: Fix old style function declarations.
* simops.c: Likewise.

[-- Attachment #2: v850.sim.patch --]
[-- Type: text/x-patch, Size: 30032 bytes --]

diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index 01a3dea..2546c58 100644
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -28,12 +28,10 @@

static const char * get_insn_name (sim_cpu *, int);

-/* For compatibility */
+/* For compatibility. */
SIM_DESC simulator;

-
-
-/* v850 interrupt model */
+/* V850 interrupt model. */

enum interrupt_type
{
@@ -48,7 +46,8 @@ enum interrupt_type
num_int_types
};

-const char *interrupt_names[] = {
+const char *interrupt_names[] =
+{
"reset",
"nmi",
"intov1",
@@ -61,9 +60,7 @@ const char *interrupt_names[] = {
};

static void
-do_interrupt (sd, data)
- SIM_DESC sd;
- void *data;
+do_interrupt (SIM_DESC sd, void *data)
{
const char **interrupt_name = (const char**)data;
enum interrupt_type inttype;
@@ -189,11 +186,10 @@ uint32 OP[4];

SIM_DESC
-sim_open (kind, cb, abfd, argv)
- SIM_OPEN_KIND kind;
- host_callback *cb;
- struct bfd *abfd;
- char **argv;
+sim_open (SIM_OPEN_KIND kind,
+ host_callback * cb,
+ struct bfd * abfd,
+ char ** argv)
{
SIM_DESC sd = sim_state_alloc (kind, cb);
int mach;
@@ -292,19 +288,16 @@ sim_open (kind, cb, abfd, argv)

void
-sim_close (sd, quitting)
- SIM_DESC sd;
- int quitting;
+sim_close (SIM_DESC sd, int quitting)
{
sim_module_uninstall (sd);
}

SIM_RC
-sim_create_inferior (sd, prog_bfd, argv, env)
- SIM_DESC sd;
- struct bfd *prog_bfd;
- char **argv;
- char **env;
+sim_create_inferior (SIM_DESC sd,
+ struct bfd * prog_bfd,
+ char ** argv,
+ char ** env)
{
memset (&State, 0, sizeof (State));
if (prog_bfd != NULL)
@@ -313,23 +306,21 @@ sim_create_inferior (sd, prog_bfd, argv, env)
}

int
-sim_fetch_register (sd, rn, memory, length)
- SIM_DESC sd;
- int rn;
- unsigned char *memory;
- int length;
+sim_fetch_register (SIM_DESC sd,
+ int rn,
+ unsigned char * memory,
+ int length)
{
*(unsigned32*)memory = H2T_4 (State.regs[rn]);
return -1;
}

int
-sim_store_register (sd, rn, memory, length)
- SIM_DESC sd;
- int rn;
- unsigned char *memory;
- int length;
+sim_store_register (SIM_DESC sd,
+ int rn,
+ unsigned char * memory,
+ int length)
{
- State.regs[rn] = T2H_4 (*(unsigned32*)memory);
+ State.regs[rn] = T2H_4 (*(unsigned32 *) memory);
return length;
}
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index bd5cf77..505b19e 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -12,7 +12,7 @@

#define WITH_TARGET_WORD_MSB 31

-
+#include "config.h"
#include "sim-basics.h"
#include "sim-signal.h"
#include "sim-fpu.h"
@@ -32,6 +32,7 @@ typedef unsigned16 uint16;
typedef signed32 int32;
typedef unsigned32 uint32;
typedef unsigned32 reg_t;
+typedef unsigned64 reg64_t;

/* The current state of the processor; registers, memory, etc. */
@@ -44,6 +45,8 @@ typedef struct _v850_regs {
reg_t mpu0_sregs[28]; /* mpu0 system registers */
reg_t mpu1_sregs[28]; /* mpu1 system registers */
reg_t fpu_sregs[28]; /* fpu system registers */
+ reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */
+ reg64_t vregs[32]; /* vector registers. */
} v850_regs;

struct _sim_cpu
@@ -126,6 +129,7 @@ nia = PC
/* new */
#define GR ((CPU)->reg.regs)
#define SR ((CPU)->reg.sregs)
+#define VR ((CPU)->reg.vregs)
#define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
#define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
#define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs)
@@ -681,4 +685,84 @@ extern int type1_regs[];
extern int type2_regs[];
extern int type3_regs[];

+#define SESR_OV (1 << 0)
+#define SESR_SOV (1 << 1)
+
+#define SESR (State.sregs[12])
+
+#define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
+#define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
+#define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
+#define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
+
+#define SAT16(X) \
+ do \
+ { \
+ signed64 z = (X); \
+ if (z > 0x7fff) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = 0x7fff; \
+ } \
+ else if (z < -0x8000) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = - 0x8000; \
+ } \
+ (X) = z; \
+ } \
+ while (0)
+
+#define SAT32(X) \
+ do \
+ { \
+ signed64 z = (X); \
+ if (z > 0x7fffffff) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = 0x7fffffff; \
+ } \
+ else if (z < -0x80000000) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = - 0x80000000; \
+ } \
+ (X) = z; \
+ } \
+ while (0)
+
+#define ABS16(X) \
+ do \
+ { \
+ signed64 z = (X) & 0xffff; \
+ if (z == 0x8000) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = 0x7fff; \
+ } \
+ else if (z & 0x8000) \
+ { \
+ z = (- z) & 0xffff; \
+ } \
+ (X) = z; \
+ } \
+ while (0)
+
+#define ABS32(X) \
+ do \
+ { \
+ signed64 z = (X) & 0xffffffff; \
+ if (z == 0x80000000) \
+ { \
+ SESR |= SESR_OV | SESR_SOV; \
+ z = 0x7fffffff; \
+ } \
+ else if (z & 0x80000000) \
+ { \
+ z = (- z) & 0xffffffff; \
+ } \
+ (X) = z; \
+ } \
+ while (0)
+
#endif
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index da6da59..b8b3856 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -55,20 +55,16 @@ int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
#endif

-unsigned32 trace_values[3];
-int trace_num_values;
-unsigned32 trace_pc;
-const char *trace_name;
-int trace_module;
+unsigned32 trace_values[3];
+int trace_num_values;
+unsigned32 trace_pc;
+const char * trace_name;
+int trace_module;

void
-trace_input (name, type, size)
- char *name;
- enum op_types type;
- int size;
+trace_input (char *name, enum op_types type, int size)
{
-
if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
return;

@@ -226,14 +222,13 @@ trace_result (int has_result, unsigned32 result)

/* append any result to the end of the buffer */
if (has_result)
- sprintf (chp, " :: 0x%.8lx", (unsigned long)result);
+ sprintf (chp, " :: 0x%.8lx", (unsigned long) result);

- trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, buf);
+ trace_generic (simulator, STATE_CPU (simulator, 0), trace_module, "%s", buf);
}

void
-trace_output (result)
- enum op_types result;
+trace_output (enum op_types result)
{
if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
return;
@@ -396,32 +391,34 @@ Multiply64 (int sign, unsigned long op0)
}

\f
-/* Read a null terminated string from memory, return in a buffer */
+/* Read a null terminated string from memory, return in a buffer. */
+
static char *
-fetch_str (sd, addr)
- SIM_DESC sd;
- address_word addr;
+fetch_str (SIM_DESC sd, address_word addr)
{
char *buf;
int nr = 0;
+
while (sim_core_read_1 (STATE_CPU (sd, 0),
PC, read_map, addr + nr) != 0)
nr++;
+
buf = NZALLOC (char, nr + 1);
- sim_read (simulator, addr, buf, nr);
+ sim_read (simulator, addr, (unsigned char *) buf, nr);
+
return buf;
}

/* Read a null terminated argument vector from memory, return in a
- buffer */
+ buffer. */
+
static char **
-fetch_argv (sd, addr)
- SIM_DESC sd;
- address_word addr;
+fetch_argv (SIM_DESC sd, address_word addr)
{
int max_nr = 64;
int nr = 0;
char **buf = xmalloc (max_nr * sizeof (char*));
+
while (1)
{
unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
@@ -442,7 +439,7 @@ fetch_argv (sd, addr)
\f
/* sst.b */
int
-OP_380 ()
+OP_380 (void)
{
trace_input ("sst.b", OP_STORE16, 1);

@@ -455,7 +452,7 @@ OP_380 ()

/* sst.h */
int
-OP_480 ()
+OP_480 (void)
{
trace_input ("sst.h", OP_STORE16, 2);

@@ -468,7 +465,7 @@ OP_480 ()

/* sst.w */
int
-OP_501 ()
+OP_501 (void)
{
trace_input ("sst.w", OP_STORE16, 4);

@@ -481,7 +478,7 @@ OP_501 ()

/* ld.b */
int
-OP_700 ()
+OP_700 (void)
{
int adr;

@@ -498,7 +495,7 @@ OP_700 ()

/* ld.h */
int
-OP_720 ()
+OP_720 (void)
{
int adr;

@@ -516,7 +513,7 @@ OP_720 ()

/* ld.w */
int
-OP_10720 ()
+OP_10720 (void)
{
int adr;

@@ -534,7 +531,7 @@ OP_10720 ()

/* st.b */
int
-OP_740 ()
+OP_740 (void)
{
trace_input ("st.b", OP_STORE32, 1);

@@ -547,7 +544,7 @@ OP_740 ()

/* st.h */
int
-OP_760 ()
+OP_760 (void)
{
int adr;

@@ -565,7 +562,7 @@ OP_760 ()

/* st.w */
int
-OP_10760 ()
+OP_10760 (void)
{
int adr;

@@ -583,7 +580,7 @@ OP_10760 ()

/* add reg, reg */
int
-OP_1C0 ()
+OP_1C0 (void)
{
unsigned int op0, op1, result, z, s, cy, ov;

@@ -615,7 +612,7 @@ OP_1C0 ()

/* add sign_extend(imm5), reg */
int
-OP_240 ()
+OP_240 (void)
{
unsigned int op0, op1, result, z, s, cy, ov;
int temp;
@@ -647,7 +644,7 @@ OP_240 ()

/* addi sign_extend(imm16), reg, reg */
int
-OP_600 ()
+OP_600 (void)
{
unsigned int op0, op1, result, z, s, cy, ov;

@@ -678,7 +675,7 @@ OP_600 ()

/* sub reg1, reg2 */
int
-OP_1A0 ()
+OP_1A0 (void)
{
unsigned int op0, op1, result, z, s, cy, ov;

@@ -707,7 +704,7 @@ OP_1A0 ()

/* subr reg1, reg2 */
int
-OP_180 ()
+OP_180 (void)
{
unsigned int op0, op1, result, z, s, cy, ov;

@@ -736,7 +733,7 @@ OP_180 ()

/* sxh reg1 */
int
-OP_E0 ()
+OP_E0 (void)
{
trace_input ("mulh", OP_REG_REG, 0);

@@ -749,7 +746,7 @@ OP_E0 ()

/* mulh sign_extend(imm5), reg2 */
int
-OP_2E0 ()
+OP_2E0 (void)
{
trace_input ("mulh", OP_IMM_REG, 0);

@@ -762,7 +759,7 @@ OP_2E0 ()

/* mulhi imm16, reg1, reg2 */
int
-OP_6E0 ()
+OP_6E0 (void)
{
trace_input ("mulhi", OP_IMM16_REG_REG, 0);

@@ -775,7 +772,7 @@ OP_6E0 ()

/* cmp reg, reg */
int
-OP_1E0 ()
+OP_1E0 (void)
{
unsigned int op0, op1, result, z, s, cy, ov;

@@ -803,7 +800,7 @@ OP_1E0 ()

/* cmp sign_extend(imm5), reg */
int
-OP_260 ()
+OP_260 (void)
{
unsigned int op0, op1, result, z, s, cy, ov;
int temp;
@@ -833,7 +830,7 @@ OP_260 ()

/* setf cccc,reg2 */
int
-OP_7E0 ()
+OP_7E0 (void)
{
trace_input ("setf", OP_EX1, 0);

@@ -846,7 +843,7 @@ OP_7E0 ()

/* satadd reg,reg */
int
-OP_C0 ()
+OP_C0 (void)
{
unsigned int op0, op1, result, z, s, cy, ov, sat;

@@ -894,7 +891,7 @@ OP_C0 ()

/* satadd sign_extend(imm5), reg */
int
-OP_220 ()
+OP_220 (void)
{
unsigned int op0, op1, result, z, s, cy, ov, sat;

@@ -945,7 +942,7 @@ OP_220 ()

/* satsub reg1, reg2 */
int
-OP_A0 ()
+OP_A0 (void)
{
unsigned int op0, op1, result, z, s, cy, ov, sat;

@@ -993,7 +990,7 @@ OP_A0 ()

/* satsubi sign_extend(imm16), reg */
int
-OP_660 ()
+OP_660 (void)
{
unsigned int op0, op1, result, z, s, cy, ov, sat;
int temp;
@@ -1044,7 +1041,7 @@ OP_660 ()

/* satsubr reg,reg */
int
-OP_80 ()
+OP_80 (void)
{
unsigned int op0, op1, result, z, s, cy, ov, sat;

@@ -1093,7 +1090,7 @@ OP_80 ()

/* tst reg,reg */
int
-OP_160 ()
+OP_160 (void)
{
unsigned int op0, op1, result, z, s;

@@ -1118,7 +1115,7 @@ OP_160 ()

/* mov sign_extend(imm5), reg */
int
-OP_200 ()
+OP_200 (void)
{
int value = SEXT5 (OP[0]);

@@ -1133,7 +1130,7 @@ OP_200 ()

/* movhi imm16, reg, reg */
int
-OP_640 ()
+OP_640 (void)
{
trace_input ("movhi", OP_UIMM16_REG_REG, 16);

@@ -1146,7 +1143,7 @@ OP_640 ()

/* sar zero_extend(imm5),reg1 */
int
-OP_2A0 ()
+OP_2A0 (void)
{
unsigned int op0, op1, result, z, s, cy;

@@ -1172,7 +1169,7 @@ OP_2A0 ()

/* sar reg1, reg2 */
int
-OP_A007E0 ()
+OP_A007E0 (void)
{
unsigned int op0, op1, result, z, s, cy;

@@ -1199,7 +1196,7 @@ OP_A007E0 ()

/* shl zero_extend(imm5),reg1 */
int
-OP_2C0 ()
+OP_2C0 (void)
{
unsigned int op0, op1, result, z, s, cy;

@@ -1225,7 +1222,7 @@ OP_2C0 ()

/* shl reg1, reg2 */
int
-OP_C007E0 ()
+OP_C007E0 (void)
{
unsigned int op0, op1, result, z, s, cy;

@@ -1251,7 +1248,7 @@ OP_C007E0 ()

/* shr zero_extend(imm5),reg1 */
int
-OP_280 ()
+OP_280 (void)
{
unsigned int op0, op1, result, z, s, cy;

@@ -1277,7 +1274,7 @@ OP_280 ()

/* shr reg1, reg2 */
int
-OP_8007E0 ()
+OP_8007E0 (void)
{
unsigned int op0, op1, result, z, s, cy;

@@ -1303,7 +1300,7 @@ OP_8007E0 ()

/* or reg, reg */
int
-OP_100 ()
+OP_100 (void)
{
unsigned int op0, op1, result, z, s;

@@ -1329,7 +1326,7 @@ OP_100 ()

/* ori zero_extend(imm16), reg, reg */
int
-OP_680 ()
+OP_680 (void)
{
unsigned int op0, op1, result, z, s;

@@ -1353,7 +1350,7 @@ OP_680 ()

/* and reg, reg */
int
-OP_140 ()
+OP_140 (void)
{
unsigned int op0, op1, result, z, s;

@@ -1379,7 +1376,7 @@ OP_140 ()

/* andi zero_extend(imm16), reg, reg */
int
-OP_6C0 ()
+OP_6C0 (void)
{
unsigned int result, z;

@@ -1403,7 +1400,7 @@ OP_6C0 ()

/* xor reg, reg */
int
-OP_120 ()
+OP_120 (void)
{
unsigned int op0, op1, result, z, s;

@@ -1429,7 +1426,7 @@ OP_120 ()

/* xori zero_extend(imm16), reg, reg */
int
-OP_6A0 ()
+OP_6A0 (void)
{
unsigned int op0, op1, result, z, s;

@@ -1453,7 +1450,7 @@ OP_6A0 ()

/* not reg1, reg2 */
int
-OP_20 ()
+OP_20 (void)
{
unsigned int op0, result, z, s;

@@ -1477,7 +1474,7 @@ OP_20 ()

/* set1 */
int
-OP_7C0 ()
+OP_7C0 (void)
{
unsigned int op0, op1, op2;
int temp;
@@ -1500,7 +1497,7 @@ OP_7C0 ()

/* not1 */
int
-OP_47C0 ()
+OP_47C0 (void)
{
unsigned int op0, op1, op2;
int temp;
@@ -1523,7 +1520,7 @@ OP_47C0 ()

/* clr1 */
int
-OP_87C0 ()
+OP_87C0 (void)
{
unsigned int op0, op1, op2;
int temp;
@@ -1546,7 +1543,7 @@ OP_87C0 ()

/* tst1 */
int
-OP_C7C0 ()
+OP_C7C0 (void)
{
unsigned int op0, op1, op2;
int temp;
@@ -1567,7 +1564,7 @@ OP_C7C0 ()

/* di */
int
-OP_16007E0 ()
+OP_16007E0 (void)
{
trace_input ("di", OP_NONE, 0);
PSW |= PSW_ID;
@@ -1578,7 +1575,7 @@ OP_16007E0 ()

/* ei */
int
-OP_16087E0 ()
+OP_16087E0 (void)
{
trace_input ("ei", OP_NONE, 0);
PSW &= ~PSW_ID;
@@ -1589,7 +1586,7 @@ OP_16087E0 ()

/* halt */
int
-OP_12007E0 ()
+OP_12007E0 (void)
{
trace_input ("halt", OP_NONE, 0);
/* FIXME this should put processor into a mode where NMI still handled */
@@ -1601,7 +1598,7 @@ OP_12007E0 ()

/* trap */
int
-OP_10007E0 ()
+OP_10007E0 (void)
{
trace_input ("trap", OP_TRAP, 0);
trace_output (OP_TRAP);
@@ -1685,7 +1682,7 @@ OP_10007E0 ()
buf = PARM1;
RETVAL = pipe (host_fd);
SW (buf, host_fd[0]);
- buf += sizeof(uint16);
+ buf += sizeof (uint16);
SW (buf, host_fd[1]);
RETERR = errno;
}
@@ -1712,7 +1709,7 @@ OP_10007E0 ()
{
char *buf = zalloc (PARM3);
RETVAL = sim_io_read (simulator, PARM1, buf, PARM3);
- sim_write (simulator, PARM2, buf, PARM3);
+ sim_write (simulator, PARM2, (unsigned char *) buf, PARM3);
free (buf);
if ((int) RETVAL < 0)
RETERR = sim_io_get_errno (simulator);
@@ -1724,7 +1721,7 @@ OP_10007E0 ()
case TARGET_SYS_write:
{
char *buf = zalloc (PARM3);
- sim_read (simulator, PARM2, buf, PARM3);
+ sim_read (simulator, PARM2, (unsigned char *) buf, PARM3);
if (PARM1 == 1)
RETVAL = sim_io_write_stdout (simulator, buf, PARM3);
else
@@ -2858,7 +2855,8 @@ OP_307E0 (void)
sim_fpu_status_denorm = 16384, ----U (sim spec.)
*/

-void update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigned int double_op_p)
+void
+update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigned int double_op_p)
{
unsigned int fpsr = FPSR & mask;

@@ -2911,15 +2909,14 @@ void update_fpsr (SIM_DESC sd, sim_fpu_status status, unsigned int mask, unsigne
FPSR &= ~FPSR_XC;
FPSR |= flags;

- SignalExceptionFPE(sd, double_op_p);
+ SignalExceptionFPE (sd, double_op_p);
}
}

-/*
- exception
-*/
+/* Exception. */

-void SignalException(SIM_DESC sd)
+void
+SignalException (SIM_DESC sd)
{
if (MPM & MPM_AUE)
{
@@ -2927,7 +2924,8 @@ void SignalException(SIM_DESC sd)
}
}

-void SignalExceptionFPE(SIM_DESC sd, unsigned int double_op_p)
+void
+SignalExceptionFPE (SIM_DESC sd, unsigned int double_op_p)
{
if (((PSW & (PSW_NP|PSW_ID)) == 0)
|| !(FPSR & (double_op_p ? FPSR_DEM : FPSR_SEM)))
@@ -2939,12 +2937,12 @@ void SignalExceptionFPE(SIM_DESC sd, unsigned int double_op_p)
PSW |= (PSW_EP | PSW_ID);
PC = 0x70;

- SignalException(sd);
+ SignalException (sd);
}
}

-
-void check_invalid_snan(SIM_DESC sd, sim_fpu_status status, unsigned int double_op_p)
+void
+check_invalid_snan (SIM_DESC sd, sim_fpu_status status, unsigned int double_op_p)
{
if ((FPSR & FPSR_XEI)
&& (status & sim_fpu_status_invalid_snan))
@@ -2952,22 +2950,23 @@ void check_invalid_snan(SIM_DESC sd, sim_fpu_status status, unsigned int double_
FPSR &= ~FPSR_XC;
FPSR |= FPSR_XCV;
FPSR |= FPSR_XPV;
- SignalExceptionFPE(sd, double_op_p);
+ SignalExceptionFPE (sd, double_op_p);
}
}

-int v850_float_compare(SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p)
+int
+v850_float_compare (SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p)
{
int result = -1;

- if (sim_fpu_is_nan(&wop1) || sim_fpu_is_nan(&wop2))
+ if (sim_fpu_is_nan (&wop1) || sim_fpu_is_nan (&wop2))
{
if (cmp & 0x8)
{
if (FPSR & FPSR_XEV)
{
FPSR |= FPSR_XCV | FPSR_XPV;
- SignalExceptionFPE(sd, double_op_p);
+ SignalExceptionFPE (sd, double_op_p);
}
}

@@ -3022,11 +3021,11 @@ int v850_float_compare(SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int dou
result = 1;
break;
default:
- abort();
+ abort ();
}
}
- else if (sim_fpu_is_infinity(&wop1) && sim_fpu_is_infinity(&wop2)
- && sim_fpu_sign(&wop1) == sim_fpu_sign(&wop2))
+ else if (sim_fpu_is_infinity (&wop1) && sim_fpu_is_infinity (&wop2)
+ && sim_fpu_sign (&wop1) == sim_fpu_sign (&wop2))
{
switch (cmp)
{
@@ -3079,44 +3078,45 @@ int v850_float_compare(SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int dou
result = 1;
break;
default:
- abort();
+ abort ();
}
}
else
{
int gt = 0,lt = 0,eq = 0, status;

- status = sim_fpu_cmp( &wop1, &wop2 );
-
- switch (status) {
- case SIM_FPU_IS_SNAN:
- case SIM_FPU_IS_QNAN:
- abort();
- break;
-
- case SIM_FPU_IS_NINF:
- lt = 1;
- break;
- case SIM_FPU_IS_PINF:
- gt = 1;
- break;
- case SIM_FPU_IS_NNUMBER:
- lt = 1;
- break;
- case SIM_FPU_IS_PNUMBER:
- gt = 1;
- break;
- case SIM_FPU_IS_NDENORM:
- lt = 1;
- break;
- case SIM_FPU_IS_PDENORM:
- gt = 1;
- break;
- case SIM_FPU_IS_NZERO:
- case SIM_FPU_IS_PZERO:
- eq = 1;
- break;
- }
+ status = sim_fpu_cmp (&wop1, &wop2);
+
+ switch (status)
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_QNAN:
+ abort ();
+ break;
+
+ case SIM_FPU_IS_NINF:
+ lt = 1;
+ break;
+ case SIM_FPU_IS_PINF:
+ gt = 1;
+ break;
+ case SIM_FPU_IS_NNUMBER:
+ lt = 1;
+ break;
+ case SIM_FPU_IS_PNUMBER:
+ gt = 1;
+ break;
+ case SIM_FPU_IS_NDENORM:
+ lt = 1;
+ break;
+ case SIM_FPU_IS_PDENORM:
+ gt = 1;
+ break;
+ case SIM_FPU_IS_NZERO:
+ case SIM_FPU_IS_PZERO:
+ eq = 1;
+ break;
+ }

switch (cmp)
{
@@ -3171,11 +3171,12 @@ int v850_float_compare(SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int dou
}
}

- ASSERT(result != -1);
+ ASSERT (result != -1);
return result;
}

-void v850_div(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
+void
+v850_div (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
{
signed long int quotient;
signed long int remainder;
@@ -3186,7 +3187,7 @@ void v850_div(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2
/* Compute the result. */
divide_by = op0;
divide_this = op1;
-
+
if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
{
overflow = TRUE;
@@ -3207,7 +3208,8 @@ void v850_div(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2
*op3p = remainder;
}

-void v850_divu(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
+void
+v850_divu (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p, unsigned int *op3p)
{
unsigned long int quotient;
unsigned long int remainder;
@@ -3240,8 +3242,8 @@ void v850_divu(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op
*op3p = remainder;
}

-
-void v850_sar(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
+void
+v850_sar (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
{
unsigned int result, z, s, cy;

@@ -3261,7 +3263,8 @@ void v850_sar(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2
*op2p = result;
}

-void v850_shl(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
+void
+v850_shl (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
{
unsigned int result, z, s, cy;

@@ -3331,7 +3334,8 @@ v850_bins (SIM_DESC sd, unsigned int source, unsigned int lsb, unsigned int msb,
* dest = result;
}

-void v850_shr(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
+void
+v850_shr (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
{
unsigned int result, z, s, cy;

@@ -3351,7 +3355,8 @@ void v850_shr(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2
*op2p = result;
}

-void v850_satadd(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
+void
+v850_satadd (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
{
unsigned int result, z, s, cy, ov, sat;

@@ -3386,7 +3391,8 @@ void v850_satadd(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *
*op2p = result;
}

-void v850_satsub(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
+void
+v850_satsub (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p)
{
unsigned int result, z, s, cy, ov, sat;

@@ -3423,10 +3429,9 @@ void v850_satsub(SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *
}

unsigned32
-load_data_mem(sd, addr, len)
- SIM_DESC sd;
- SIM_ADDR addr;
- int len;
+load_data_mem (SIM_DESC sd,
+ SIM_ADDR addr,
+ int len)
{
uint32 data;

@@ -3451,74 +3456,74 @@ load_data_mem(sd, addr, len)
}

void
-store_data_mem(sd, addr, len, data)
- SIM_DESC sd;
- SIM_ADDR addr;
- int len;
- unsigned32 data;
+store_data_mem (SIM_DESC sd,
+ SIM_ADDR addr,
+ int len,
+ unsigned32 data)
{
switch (len)
{
case 1:
- store_mem(addr, 1, data);
+ store_mem (addr, 1, data);
break;
case 2:
- store_mem(addr, 2, data);
+ store_mem (addr, 2, data);
break;
case 4:
- store_mem(addr, 4, data);
+ store_mem (addr, 4, data);
break;
default:
abort ();
}
}

-int mpu_load_mem_test(SIM_DESC sd, unsigned int addr, int size, int base_reg)
+int
+mpu_load_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg)
{
int result = 1;

if (PSW & PSW_DMP)
{
- if (IPE0 && addr >= IPA2ADDR(IPA0L) && addr <= IPA2ADDR(IPA0L) && IPR0)
+ if (IPE0 && addr >= IPA2ADDR (IPA0L) && addr <= IPA2ADDR (IPA0L) && IPR0)
{
/* text area */
}
- else if (IPE1 && addr >= IPA2ADDR(IPA1L) && addr <= IPA2ADDR(IPA1L) && IPR1)
+ else if (IPE1 && addr >= IPA2ADDR (IPA1L) && addr <= IPA2ADDR (IPA1L) && IPR1)
{
/* text area */
}
- else if (IPE2 && addr >= IPA2ADDR(IPA2L) && addr <= IPA2ADDR(IPA2L) && IPR2)
+ else if (IPE2 && addr >= IPA2ADDR (IPA2L) && addr <= IPA2ADDR (IPA2L) && IPR2)
{
/* text area */
}
- else if (IPE3 && addr >= IPA2ADDR(IPA3L) && addr <= IPA2ADDR(IPA3L) && IPR3)
+ else if (IPE3 && addr >= IPA2ADDR (IPA3L) && addr <= IPA2ADDR (IPA3L) && IPR3)
{
/* text area */
}
- else if (addr >= PPA2ADDR(PPA & ~PPM) && addr <= DPA2ADDR(PPA | PPM))
+ else if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
{
/* preifarallel area */
}
- else if (addr >= PPA2ADDR(SPAL) && addr <= DPA2ADDR(SPAU))
+ else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU))
{
/* stack area */
}
- else if (DPE0 && addr >= DPA2ADDR(DPA0L) && addr <= DPA2ADDR(DPA0L) && DPR0
+ else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPR0
&& ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
{
/* data area */
}
- else if (DPE1 && addr >= DPA2ADDR(DPA1L) && addr <= DPA2ADDR(DPA1L) && DPR1
+ else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPR1
&& ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
{
/* data area */
}
- else if (DPE2 && addr >= DPA2ADDR(DPA2L) && addr <= DPA2ADDR(DPA2L) && DPR2
+ else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPR2
&& ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
{
/* data area */
}
- else if (DPE3 && addr >= DPA2ADDR(DPA3L) && addr <= DPA2ADDR(DPA3L) && DPR3
+ else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPR3
&& ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
{
/* data area */
@@ -3533,7 +3538,7 @@ int mpu_load_mem_test(SIM_DESC sd, unsigned int addr, int size, int base_reg)

PC = 0x30;

- SignalException(sd);
+ SignalException (sd);
result = 0;
}
}
@@ -3541,43 +3546,44 @@ int mpu_load_mem_test(SIM_DESC sd, unsigned int addr, int size, int base_reg)
return result;
}

-int mpu_store_mem_test(SIM_DESC sd, unsigned int addr, int size, int base_reg)
+int
+mpu_store_mem_test (SIM_DESC sd, unsigned int addr, int size, int base_reg)
{
int result = 1;

if (PSW & PSW_DMP)
{
- if (addr >= PPA2ADDR(PPA & ~PPM) && addr <= DPA2ADDR(PPA | PPM))
+ if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
{
/* preifarallel area */
}
- else if (addr >= PPA2ADDR(SPAL) && addr <= DPA2ADDR(SPAU))
+ else if (addr >= PPA2ADDR (SPAL) && addr <= DPA2ADDR (SPAU))
{
/* stack area */
}
- else if (DPE0 && addr >= DPA2ADDR(DPA0L) && addr <= DPA2ADDR(DPA0L) && DPW0
+ else if (DPE0 && addr >= DPA2ADDR (DPA0L) && addr <= DPA2ADDR (DPA0L) && DPW0
&& ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
{
/* data area */
}
- else if (DPE1 && addr >= DPA2ADDR(DPA1L) && addr <= DPA2ADDR(DPA1L) && DPW1
+ else if (DPE1 && addr >= DPA2ADDR (DPA1L) && addr <= DPA2ADDR (DPA1L) && DPW1
&& ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
{
/* data area */
}
- else if (DPE2 && addr >= DPA2ADDR(DPA2L) && addr <= DPA2ADDR(DPA2L) && DPW2
+ else if (DPE2 && addr >= DPA2ADDR (DPA2L) && addr <= DPA2ADDR (DPA2L) && DPW2
&& ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
{
/* data area */
}
- else if (DPE3 && addr >= DPA2ADDR(DPA3L) && addr <= DPA2ADDR(DPA3L) && DPW3
+ else if (DPE3 && addr >= DPA2ADDR (DPA3L) && addr <= DPA2ADDR (DPA3L) && DPW3
&& ((SPAL & SPAL_SPS) ? base_reg == SP_REGNO : 1))
{
/* data area */
}
else
{
- if (addr >= PPA2ADDR(PPA & ~PPM) && addr <= DPA2ADDR(PPA | PPM))
+ if (addr >= PPA2ADDR (PPA & ~PPM) && addr <= DPA2ADDR (PPA | PPM))
{
FEIC = 0x432;
VPTID = TID;
diff --git a/sim/v850/v850-dc b/sim/v850/v850-dc
index 1a90363..9189833 100644
--- a/sim/v850/v850-dc
+++ b/sim/v850/v850-dc
@@ -64,3 +64,9 @@
switch,combine : 4 : 0 : : : : 0 :VI : v850e2v3
switch,combine : 4 : 0 : : : : 0 :VI : v850e3v5
switch,combine : 10 : 0 : : : : 1 :F_I,XI : v850e3v5
+
+# for sasf, vadd.h
+ switch,combine : 10 : 0 : : : : 1 :C,IX : v850e3v5
+ switch,combine : 10 : 0 : : : : 1 :C,XII : v850e3v5
+ switch,combine : 15 : 0 : : : : 0 :C : v850e3v5
+ switch,combine : 10 : 0 : : : : 1 :C,XI : v850e3v5
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index 0270963..41a9075 100644
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -2561,7 +2561,7 @@ rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl
*v850e3v5
"cvtf.dl r<reg2e>, r<reg3e>"
{
- unsigned64 ans;
+ signed64 ans;
sim_fpu wop;
sim_fpu_status status;

@@ -2604,7 +2604,7 @@ rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw
*v850e3v5
"cvtf.dw r<reg2e>, r<reg3>"
{
- uint32 ans;
+ int32 ans;
sim_fpu wop;
sim_fpu_status status;

@@ -2712,7 +2712,7 @@ rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw
*v850e3v5
"cvtf.sw r<reg2>, r<reg3>"
{
- uint32 ans;
+ int32 ans;
sim_fpu wop;
sim_fpu_status status;

@@ -3471,7 +3471,7 @@ rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul
*v850e3v5
"trncf.dul r<reg2e>, r<reg3e>"
{
- signed64 ans;
+ unsigned64 ans;
sim_fpu wop;
sim_fpu_status status;

@@ -3493,7 +3493,7 @@ rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
*v850e3v5
"trncf.dw r<reg2e>, r<reg3>"
{
- uint32 ans;
+ int32 ans;
sim_fpu wop;
sim_fpu_status status;

@@ -3555,7 +3555,7 @@ rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul
*v850e3v5
"trncf.sul r<reg2>, r<reg3e>"
{
- signed64 ans;
+ unsigned64 ans;
sim_fpu wop;
sim_fpu_status status;

@@ -3575,7 +3575,7 @@ rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
*v850e3v5
"trncf.sw r<reg2>, r<reg3>"
{
- uint32 ans;
+ int32 ans;
sim_fpu wop;
sim_fpu_status status;