From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20780 invoked by alias); 22 Feb 2015 04:40:19 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 20762 invoked by uid 89); 22 Feb 2015 04:40:17 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,SPF_PASS,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: smtp.gentoo.org Received: from smtp.gentoo.org (HELO smtp.gentoo.org) (140.211.166.183) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Sun, 22 Feb 2015 04:40:15 +0000 Received: from vapier (localhost [127.0.0.1]) by smtp.gentoo.org (Postfix) with SMTP id 7FF283408B7; Sun, 22 Feb 2015 04:40:12 +0000 (UTC) Date: Sun, 22 Feb 2015 04:40:00 -0000 From: Mike Frysinger To: Jiri Gaisler Cc: gdb-patches@sourceware.org Subject: Re: [PATCH 04/23] sim/erc32: Add FPU support on x86_64 hosts. Message-ID: <20150222044012.GD25220@vapier> Mail-Followup-To: Jiri Gaisler , gdb-patches@sourceware.org References: <1424159099-5148-1-git-send-email-jiri@gaisler.se> <1424159099-5148-5-git-send-email-jiri@gaisler.se> <20150217090529.GJ20008@vapier> <54E64B65.4050906@gaisler.se> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="2Z2K0IlrPCVsbNpk" Content-Disposition: inline In-Reply-To: <54E64B65.4050906@gaisler.se> X-IsSubscribed: yes X-SW-Source: 2015-02/txt/msg00626.txt.bz2 --2Z2K0IlrPCVsbNpk Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Content-length: 1082 On 19 Feb 2015 21:45, Jiri Gaisler wrote: > On 02/17/2015 10:05 AM, Mike Frysinger wrote: > > On 17 Feb 2015 08:44, Jiri Gaisler wrote: > >> * float.c (get_accex) access FPU control and status words on x64 > >=20 > > shouldn't you gut this file and use instead for a portable met= hod ? > > http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/fenv.h.html > >=20 > > at the very least, you could cut over to ... >=20 > I will switch to fenv.h, but this will produce less accurate results > on Intel hardware. double on SPARC V8 has 53-bit mantissa while Intel has > both 53- and 64-bit, and 64-bit is default. To get accurate SPARC V8 FPU > operations, the Intel FPU should be switched to 53-bit, but the fenv.h > does not have an API for this. I guess we will have to live with that ... if you wanted to keep a little inline asm to just that particular bit twidd= le,=20 that should be fine. normally the sims are functional ... but i guess this part of the simulator= is=20 relying on the inaccuracies of floating point to trade for speed ? -mike --2Z2K0IlrPCVsbNpk Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature Content-length: 819 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJU6V2sAAoJEEFjO5/oN/WBtBMP/0U2HhUXwZR4WKtOXlZr9VHG LrIvPwQVosWROs7Q4BRxA/GTkyM/vsqCXb37jFCyAH8nMIoZLQbzABaaqE0syJT2 BKjsaeeTBwDGRoU49Bl275ByMOD7vs063H1vbWYgkCGWAFCbe5sEIpoYo+evHVQW OP23/Cj21kDyVY0Zta+xMEfp3mLxVCFElKfewqXrDxAjpUqyYqqOA4h/Pcq7IWXI jcfic5FQ8yy6BOrHoUb+dvrJdhLjzZEr9AdpyGfglpb1fScqcJ+oWT7l3TBQuA+C Ia6qhmshti+nd9MbN9cqKIYcHYZ6NEs2jMo7v61XpCaBkGId9LQusYOun+t18Maz LQ/A+YqBcc72McDkFXRxhXKFd/6g+LnZZKy4ef+GF1pdZGt4P8k1+6tk4LXMtfWG AdBP8sOrpehZPzuouAb19PDQuw6ZIMvq0neetXFAgqRTnizVSkw/tWa+b2YCdAoA KX1XwpoiWA1Yy47GpxaN4n935Ok/kCCWJM38ng4qgEjuVEjXyzKaRyWptx3Tk2Nv M0ioQcTMctJgSST3WcLT+GDTIP2Gehv10Di6dh+E5n+f8cJ8+6EXBiK3n5Aj7p5q +8h8Y4k6u8IwkzyTAQHNhaaBZLuwLO2XZjiIgZZqhtGSRXCRO5mDaFbjoLmuJzz7 4ZedhByZdrGDQQlr5Qko =u57d -----END PGP SIGNATURE----- --2Z2K0IlrPCVsbNpk--