Re: [PATCH V5 0/3] Intel(R) AVX-512 register support

Pedro Alves
2014-04-24T11:49:05Z

On 04/23/2014 02:02 PM, Michael Sturm wrote:
> Pedro,
>
> thanks for your review. We've addressed the comments you made regarding the
> test case and the manual content. We do agree to your comment
> regarding sharing code between GDB and GDBserver. We would prefer to
> make this change in a patch dedicated to unify XSAVE buffer access
> between GDB and GDBserver.
> Would you agree to that and approve committing this series?

Definitely. I wasn't suggesting making that as part of this patch.

Oh,

> This patch series adds support for the Intel(R) Advanced Vector Extensions 512
> (Intel(R) AVX-512) registers. Native and remote debugging are covered by this
> patch series.
>
> Intel(R) AVX-512 is an extension to AVX to support 512-bit wide SIMD registers
> in 64-bit mode (XMM0-XMM31, YMM0-YMM31, ZMM0-ZMM31). The number of available
> registers in 32-bit mode is still 8 (XMM0-7, YMM0-7, ZMM0-7). The lower
> 256-bits of the ZMM registers are aliased to the respective 256-bit YMM
> registers. The lower 128-bits are aliased to the respective 128-bit XMM
> registers.
>
> There are also 8 new, dedicated mask registers (K0-K7) in both 32-bit mode
> and 64-bit mode.
>
> For more information please see
> Intel(R) Developer Zone: Intel(R) AVX
> http://software.intel.com/en-us/intel-isa-extensions#pid-16007-1495
>
> Intel(R) Architecture Instruction Set Extensions Programming Reference:
> http://software.intel.com/en-us/file/319433-017pdf

I notice that this info is only in the series cover letter, which
never makes it to the commit log. Would you mind putting it in at
least the commit log entry of the GDB patch (tweaked a little to
not say "series")? (pre-approved, no need for another round
of review for that).

Thanks,
--
Pedro Alves