Re: [PATCH 1/4] Restrict matching add/sub sp, #imm

Will Newton
2014-07-03T08:31:11Z

On 3 July 2014 07:09, Yao Qi <yao@codesourcery.com> wrote:
> Currently, GDB matches both add/sub sp, #imm in prologue and epilogue,
> which is not very precise. On the instruction level, the immediate
> number in both instruction can't be negative, so 'sub sp, #imm' only
> appears in prologue while 'add sp, #imm' only appears in epilogue.
> Note that on assembly level, we can write 'add sp, -8', but gas will
> translate to 'sub sp, 8' instruction.
>
> This patch is to only match 'sub sp, #imm' in prologue and match
> 'add sp, #immm' in epilogue. It paves the way for the following
> patch.
>
> gdb:
>
> 2014-07-02 Yao Qi <yao@codesourcery.com>
>
> * arm-tdep.c (thumb_analyze_prologue): Don't match instruction
> 'add sp, #immm'.

One too many ms?

> (thumb_in_function_epilogue_p): Don't match 'sub sp, #imm'.
> ---
> gdb/arm-tdep.c | 15 +++++----------
> 1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
> index 8cc60a4..0fc7fc1 100644
> --- a/gdb/arm-tdep.c
> +++ b/gdb/arm-tdep.c
> @@ -737,16 +737,11 @@ thumb_analyze_prologue (struct gdbarch *gdbarch,
> pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]);
> }
> }
> - else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR
> - sub sp, #simm */
> + else if ((insn & 0xff80) == 0xb080) /* sub sp, #simm */

I wonder if we should adjust the comment to just #imm, as #simm
implies it is a signed quantity.

> {
> offset = (insn & 0x7f) << 2; /* get scaled offset */
> - if (insn & 0x80) /* Check for SUB. */
> - regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
> - -offset);
> - else
> - regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
> - offset);
> + regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM],
> + -offset);
> }
> else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */
> regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM],
> @@ -3264,7 +3259,7 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
> found_return = 1;
> else if (insn == 0x46bd) /* mov sp, r7 */
> found_stack_adjust = 1;
> - else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
> + else if ((insn & 0xff80) == 0xb000) /* add sp, imm */
> found_stack_adjust = 1;
> else if ((insn & 0xfe00) == 0xbc00) /* pop <registers> */
> {
> @@ -3324,7 +3319,7 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
>
> if (insn2 == 0x46bd) /* mov sp, r7 */
> found_stack_adjust = 1;
> - else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */
> + else if ((insn2 & 0xff80) == 0xb000) /* add sp, imm */
> found_stack_adjust = 1;
> else if ((insn2 & 0xff00) == 0xbc00) /* pop <registers> without PC */
> found_stack_adjust = 1;

Otherwise the patch looks good to me.

--
Will Newton
Toolchain Working Group, Linaro