From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7671 invoked by alias); 21 Aug 2013 14:33:47 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 7657 invoked by uid 89); 21 Aug 2013 14:33:46 -0000 X-Spam-SWARE-Status: No, score=-4.5 required=5.0 tests=AWL,BAYES_00,KHOP_THREADED,RP_MATCHES_RCVD autolearn=ham version=3.3.2 Received: from sibelius.xs4all.nl (HELO glazunov.sibelius.xs4all.nl) (83.163.83.176) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Wed, 21 Aug 2013 14:33:45 +0000 Received: from glazunov.sibelius.xs4all.nl (kettenis@localhost [127.0.0.1]) by glazunov.sibelius.xs4all.nl (8.14.5/8.14.3) with ESMTP id r7LEXb7C025240; Wed, 21 Aug 2013 16:33:37 +0200 (CEST) Received: (from kettenis@localhost) by glazunov.sibelius.xs4all.nl (8.14.5/8.14.3/Submit) id r7LEXaQ9000855; Wed, 21 Aug 2013 16:33:36 +0200 (CEST) Date: Wed, 21 Aug 2013 14:33:00 -0000 Message-Id: <201308211433.r7LEXaQ9000855@glazunov.sibelius.xs4all.nl> From: Mark Kettenis To: walfred.tedeschi@intel.com CC: tromey@redhat.com, jan.kratochvil@redhat.com, mark.kettenis@xs4all.nl, gdb-patches@sourceware.org, walfred.tedeschi@intel.com In-reply-to: <1377089148-11844-1-git-send-email-walfred.tedeschi@intel.com> (message from Walfred Tedeschi on Wed, 21 Aug 2013 14:45:41 +0200) Subject: Re: [PATCH 0/7] Intel(R) MPX registers support. References: <1377089148-11844-1-git-send-email-walfred.tedeschi@intel.com> X-SW-Source: 2013-08/txt/msg00579.txt.bz2 > From: Walfred Tedeschi > Date: Wed, 21 Aug 2013 14:45:41 +0200 > > This patch series adds support for the Intel(R) Memory Protection Extension > MPX registers. Native and remote debugging are covered by this patch. > > New registers are bound registers known as bnd register (bnd0...bnd3), a > config register bndcfgu and a status register bndstatus. Bound registers > store pointer bounds, i.e. bound limits of a pointer. Bndstatus and bndcfgu > store information of the current status and configuration of other MPX > counterparts. For more information [1][2]. > > Design notes: > Bound register are represented in hardware as two fields of 64bits each, > both in 64bit and 32bit mode. The fields are lower bound and upper bound. > Upper bound value is a complement of one value of the upper limiting > address. To take this into account the bnd0...bnd3 are created as > pseudo registers while the hardware values are stored on bnd0raw...bnd3raw. > > Ok to commit? Hi Walfred, I had a quick look at the diffs. Generally looks good. There is an issue though with how you handled the Linux-specific "orig_[er]ax" fake register in the GDB interal register mapping. Can you change things such that it remains at the very hand of the internal register file? I may not be able to do a full review of the changes in the next 2.5 weeks. A friendly reminder somewhere after Sep 9 wouldn't hurt ;). Cheers, Mark