From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15724 invoked by alias); 30 Jul 2012 15:15:50 -0000 Received: (qmail 15715 invoked by uid 22791); 30 Jul 2012 15:15:49 -0000 X-SWARE-Spam-Status: No, hits=-3.3 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,MSGID_FROM_MTA_HEADER,RCVD_IN_HOSTKARMA_W,RCVD_IN_HOSTKARMA_WL,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from e06smtp17.uk.ibm.com (HELO e06smtp17.uk.ibm.com) (195.75.94.113) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 30 Jul 2012 15:15:35 +0000 Received: from /spool/local by e06smtp17.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 30 Jul 2012 16:15:33 +0100 Received: from d06nrmr1806.portsmouth.uk.ibm.com (9.149.39.193) by e06smtp17.uk.ibm.com (192.168.101.147) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Mon, 30 Jul 2012 16:15:30 +0100 Received: from d06av02.portsmouth.uk.ibm.com (d06av02.portsmouth.uk.ibm.com [9.149.37.228]) by d06nrmr1806.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q6UFFUsC2601198 for ; Mon, 30 Jul 2012 16:15:30 +0100 Received: from d06av02.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q6UFFT2F012986 for ; Mon, 30 Jul 2012 09:15:30 -0600 Received: from tuxmaker.boeblingen.de.ibm.com (tuxmaker.boeblingen.de.ibm.com [9.152.85.9]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with SMTP id q6UFFSCS012933; Mon, 30 Jul 2012 09:15:28 -0600 Message-Id: <201207301515.q6UFFSCS012933@d06av02.portsmouth.uk.ibm.com> Received: by tuxmaker.boeblingen.de.ibm.com (sSMTP sendmail emulation); Mon, 30 Jul 2012 17:15:27 +0200 Subject: [ARM, commit, RFA 7.5] Fix HW breakpoints on unaligned addresses To: gdb-patches@sourceware.org, brobecker@adacore.com Date: Mon, 30 Jul 2012 15:15:00 -0000 From: "Ulrich Weigand" MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit x-cbid: 12073015-0542-0000-0000-0000029ADDC8 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-07/txt/msg00739.txt.bz2 Hello, the new hbreak2.exp tests are failing on ARM. It turns out that when attempting to set a HW breakpoint on an address that is not aligned to 4 bytes (on Thumb), the kernel rejects GDB's ptrace calls as invalid. After some discussion with Will Deacon (who implemented the kernel side of this interface), we've decided to fix this on the GDB side: GDB tries to align the address to 4 bytes and uses the "byte address select" feature to specify only the two upper bytes in that range. However, the kernel interface does not (yet) support this use of the BAS field. On the other hand, the kernel *does* support just specifying the unaligned address in the address field, and setting up the BAS field for a normal 2-byte access. (This use is not supported by the hardware, but will get fixed up by the kernel.) Since this alternative way is supported by all existing kernels (that support the HW breakpoint ptrace interface), and will remain supported in the future (even once kernels may start supporting more general use of the BAS field), we can fix this simply by changing GDB to use that alternative. The patch below implements this in both GDB and gdbserver. Tested on arm-linux-gnueabi (Cortex-A9), fixes the hbreak2 regressions. Committed to mainline. Joel, would this be OK for the 7.5 branch at this point? In general, what's the timeline for 7.5? I've noticed a couple of other test case regressions when testing the branch on ARM, s390, and Cell ... Bye, Ulrich ChangeLog: * arm-linux-nat.c (arm_linux_hw_breakpoint_initialize): Do not attempt to 4-byte-align HW breakpoint addresses for Thumb. gdbserver/ChangeLog: * linux-arm-low.c (arm_linux_hw_point_initialize): Do not attempt to 4-byte-align HW breakpoint addresses for Thumb. Index: gdb/arm-linux-nat.c =================================================================== RCS file: /cvs/src/src/gdb/arm-linux-nat.c,v retrieving revision 1.55 diff -u -p -r1.55 arm-linux-nat.c --- gdb/arm-linux-nat.c 6 Jul 2012 16:49:43 -0000 1.55 +++ gdb/arm-linux-nat.c 30 Jul 2012 15:00:33 -0000 @@ -896,11 +896,17 @@ arm_linux_hw_breakpoint_initialize (stru /* We have to create a mask for the control register which says which bits of the word pointed to by address to break on. */ if (arm_pc_is_thumb (gdbarch, address)) - mask = 0x3 << (address & 2); + { + mask = 0x3; + address &= ~1; + } else - mask = 0xf; + { + mask = 0xf; + address &= ~3; + } - p->address = (unsigned int) (address & ~3); + p->address = (unsigned int) address; p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); } Index: gdb/gdbserver/linux-arm-low.c =================================================================== RCS file: /cvs/src/src/gdb/gdbserver/linux-arm-low.c,v retrieving revision 1.34 diff -u -p -r1.34 linux-arm-low.c --- gdb/gdbserver/linux-arm-low.c 24 Apr 2012 15:03:43 -0000 1.34 +++ gdb/gdbserver/linux-arm-low.c 30 Jul 2012 15:00:33 -0000 @@ -474,17 +474,17 @@ arm_linux_hw_point_initialize (char type { case 2: /* 16-bit Thumb mode breakpoint */ case 3: /* 32-bit Thumb mode breakpoint */ - mask = 0x3 << (addr & 2); + mask = 0x3; + addr &= ~1; break; case 4: /* 32-bit ARM mode breakpoint */ mask = 0xf; + addr &= ~3; break; default: /* Unsupported. */ return -1; } - - addr &= ~3; } else { -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE Ulrich.Weigand@de.ibm.com