From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4069 invoked by alias); 4 May 2012 20:58:37 -0000 Received: (qmail 4057 invoked by uid 22791); 4 May 2012 20:58:36 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL,BAYES_00,RCVD_IN_HOSTKARMA_NO,TW_EG X-Spam-Check-By: sourceware.org Received: from rock.gnat.com (HELO rock.gnat.com) (205.232.38.15) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 04 May 2012 20:58:23 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by filtered-rock.gnat.com (Postfix) with ESMTP id 581501C6DD6; Fri, 4 May 2012 16:58:22 -0400 (EDT) Received: from rock.gnat.com ([127.0.0.1]) by localhost (rock.gnat.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id cmsT-CxKn7Sb; Fri, 4 May 2012 16:58:22 -0400 (EDT) Received: from joel.gnat.com (localhost.localdomain [127.0.0.1]) by rock.gnat.com (Postfix) with ESMTP id 0926D1C6DD5; Fri, 4 May 2012 16:58:21 -0400 (EDT) Received: by joel.gnat.com (Postfix, from userid 1000) id D56BF145616; Fri, 4 May 2012 13:58:18 -0700 (PDT) Date: Fri, 04 May 2012 20:58:00 -0000 From: Joel Brobecker To: "Maciej W. Rozycki" Cc: gdb-patches@sourceware.org Subject: Re: [RFA 1/2] mips: Switch inferior function calls to ON_STACK method. Message-ID: <20120504205818.GT15555@adacore.com> References: <1336071802-13599-1-git-send-email-brobecker@adacore.com> <1336071802-13599-2-git-send-email-brobecker@adacore.com> <20120503214933.GJ15555@adacore.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="fXStkuK2IQBfcDe+" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-05/txt/msg00136.txt.bz2 --fXStkuK2IQBfcDe+ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-length: 1348 Now I know why I was told you are a MIPS expert :-). I never really had the chance or need to delve into the details of any specific architecture. Even for the ia64-hpux port, I could do with just a superficial knowledge of that CPU. > * newly-added 48-bit instructions. I am wondering if this addition is going to hurt in terms of our support... From what I could tell from my mips64 manual, even on this CPU the instructions are still 32bit long... But I'm digressing, sorry. > Coincidentally all-zeroes is a 32-bit NOP instruction both in the > standard MIPS and the microMIPS mode -- there's a 16-bit encoding of NOP > in the microMIPS mode naturally as well. I'm wondering if you'd like me to rename "null_insn" into "nop_insn" in my patch. I didn't do it, because I'd expect the instruction size to depend on the mode. As of today, we know that the breakpoint we are inserting is always going to be at an even address, so it's always going to be 4 bytes. So maybe it does make sense to rename it. Let me know. > Understood, but I'd be happier if the comment you're removing or a > similar stayed in place. If by trap you mean SIGTRAP, then I think this > is not going to be the case. I think you refer to the comment from Andrew Cagney? I've put it back as is. OK to commit, modulo the possible rename above? Thanks, -- Joel --fXStkuK2IQBfcDe+ Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="mips-on-stack-v3.diff" Content-length: 2744 commit b78a75e1442a349531a017036a02f43c4df71427 Author: Joel Brobecker Date: Wed May 2 20:39:57 2012 -0400 mips: Switch inferior function calls to ON_STACK method. This patch switches the mips code to use the ON_STACK method for function calls instead of AT_SYMBOL, which we want to remove. gdb/ChangeLog: * mips-tdep.c (mips_push_dummy_code): New function. (mips_gdbarch_init): Set the gdbarch call_dummy_location to ON_STACK and install mips_push_dummy_code as our gdbarch push_dummy_code routine. diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index 9a3c7fb..5e9a6ed 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -3009,6 +3009,37 @@ mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) return align_down (addr, 16); } +/* Implement the push_dummy_code gdbarch method for mips targets. */ + +static CORE_ADDR +mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, + CORE_ADDR funaddr, struct value **args, + int nargs, struct type *value_type, + CORE_ADDR *real_pc, CORE_ADDR *bp_addr, + struct regcache *regcache) +{ + int bp_len; + gdb_byte null_insn[4] = { 0 }; + + *bp_addr = mips_frame_align (gdbarch, sp); + gdbarch_breakpoint_from_pc (gdbarch, bp_addr, &bp_len); + + /* The breakpoint layer automatically adjusts the address of + breakpoints inserted in a branch delay slot. With enough + bad luck, the 4 bytes located just before our breakpoint + instruction could look like a branch instruction, and thus + trigger the adjustement, and break the function call entirely. + So, we reserve those 4 bytes and write a null instruction + to prevent that from happening. */ + write_memory (*bp_addr - bp_len, null_insn, sizeof (null_insn)); + sp = mips_frame_align (gdbarch, *bp_addr - 2 * bp_len); + + /* Inferior resumes at the function entry point. */ + *real_pc = funaddr; + + return sp; +} + static CORE_ADDR mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, @@ -6909,7 +6940,8 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* NOTE: cagney/2003-08-05: Eventually call dummy location will be replaced by a command, and all targets will default to on stack (regardless of the stack's execute status). */ - set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); + set_gdbarch_call_dummy_location (gdbarch, ON_STACK); + set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); set_gdbarch_frame_align (gdbarch, mips_frame_align); set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); --fXStkuK2IQBfcDe+--