Now I know why I was told you are a MIPS expert :-). I never really
had the chance or need to delve into the details of any specific
architecture. Even for the ia64-hpux port, I could do with just
a superficial knowledge of that CPU.

> * newly-added 48-bit instructions.

I am wondering if this addition is going to hurt in terms of our
support...  From what I could tell from my mips64 manual, even
on this CPU the instructions are still 32bit long... But I'm
digressing, sorry.

>  Coincidentally all-zeroes is a 32-bit NOP instruction both in the 
> standard MIPS and the microMIPS mode -- there's a 16-bit encoding of NOP 
> in the microMIPS mode naturally as well.

I'm wondering if you'd like me to rename "null_insn" into "nop_insn"
in my patch. I didn't do it, because I'd expect the instruction size
to depend on the mode. As of today, we know that the breakpoint we
are inserting is always going to be at an even address, so it's always
going to be 4 bytes. So maybe it does make sense to rename it. Let
me know.

>  Understood, but I'd be happier if the comment you're removing or a 
> similar stayed in place.  If by trap you mean SIGTRAP, then I think this 
> is not going to be the case.

I think you refer to the comment from Andrew Cagney? I've put it back
as is.

OK to commit, modulo the possible rename above?

Thanks,
-- 
Joel