Re: Please fix regressions from your sim changes

Mike Frysinger
2012-03-19T17:23:08Z

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On Monday 19 March 2012 02:28:49 Hans-Peter Nilsson wrote:
> For mips-elf, there's just

mips-elf is passing for me

> From sim.log it seems just some expected patterns need updating.
>
> Executing on host: mips-elf-ld hilo-hazard-1.s.o -N -Ttext=0x80010000 -o
> hilo-hazard-1.s.x (timeout = 300)
> /tmp/hpautotest-sim/mips-elf/sim/mips/run hilo-hazard-1.s.x
> HILO: MULT: OP at 0x80010048 too close to MF at 0x80010044
>
> output: HILO: MULT: OP at 0x80010048 too close to MF at 0x80010044
>
>
> pattern: HILO: * too close to MF at *\
> \
> program stopped*\
>
> FAIL: mips1 hilo-hazard-1.s (execution)

the glob should eat the new signal string

> For cris-elf, there's quite a bit more, three variants AFAICT;
> three "signals" lost.

patch attached should fix that

> And really, why removing the "program stopped with signal"
> common part? I see no reason to not just adding it back.

it wasn't removed. the signal is now additionally being decoded.

before: program stopped with signal 5.
after: program stopped with signal 5 (Trace/breakpoint trap).
-mike

[-- Attachment #1.2: sim-cris-testsuite.patch --]
[-- Type: text/x-patch, Size: 13526 bytes --]

--- sim/testsuite/sim/cris/asm/addqpc.ms
+++ sim/testsuite/sim/cris/asm/addqpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/boundmv32.ms
+++ sim/testsuite/sim/cris/asm/boundmv32.ms
@@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
-# output: program stopped with signal 4.\n
+# output: program stopped with signal 4 (*).\n
.include "testutils.inc"

; Check that bound with a memory operand is invalid.
--- sim/testsuite/sim/cris/asm/fidxd.ms
+++ sim/testsuite/sim/cris/asm/fidxd.ms
@@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
-# output: FIDXD isn't implemented\nprogram stopped with signal 5.\n
+# output: FIDXD isn't implemented\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/fidxi.ms
+++ sim/testsuite/sim/cris/asm/fidxi.ms
@@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
-# output: FIDXI isn't implemented\nprogram stopped with signal 5.\n
+# output: FIDXI isn't implemented\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/ftagd.ms
+++ sim/testsuite/sim/cris/asm/ftagd.ms
@@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
-# output: FTAGD isn't implemented\nprogram stopped with signal 5.\n
+# output: FTAGD isn't implemented\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/ftagi.ms
+++ sim/testsuite/sim/cris/asm/ftagi.ms
@@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
-# output: FTAGI isn't implemented\nprogram stopped with signal 5.\n
+# output: FTAGI isn't implemented\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/halt.ms
+++ sim/testsuite/sim/cris/asm/halt.ms
@@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
-# output: HALT isn't implemented\nprogram stopped with signal 5.\n
+# output: HALT isn't implemented\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/io6.ms
+++ sim/testsuite/sim/cris/asm/io6.ms
@@ -4,7 +4,7 @@
# xerror:
# output: b1e\n
# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n
-# output: program stopped with signal 11.\n
+# output: program stopped with signal 11 (*).\n

; Check that invalid access to the simulator area is recognized.
; "FAIL" area.
--- sim/testsuite/sim/cris/asm/io7.ms
+++ sim/testsuite/sim/cris/asm/io7.ms
@@ -4,7 +4,7 @@
# xerror:
# output: ce11d0c\n
# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n
-# output: program stopped with signal 11.\n
+# output: program stopped with signal 11 (*).\n

; Check that invalid access to the simulator area is recognized.
; "PASS" area.
--- sim/testsuite/sim/cris/asm/io8.ms
+++ sim/testsuite/sim/cris/asm/io8.ms
@@ -3,7 +3,7 @@
# xerror:
# output: b1e\n
# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n
-# output: program stopped with signal 11.\n
+# output: program stopped with signal 11 (*).\n

; Check invalid access valid with --cris-900000xx.
; "FAIL" area.
--- sim/testsuite/sim/cris/asm/io9.ms
+++ sim/testsuite/sim/cris/asm/io9.ms
@@ -3,7 +3,7 @@
# xerror:
# output: ce11d0c\n
# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n
-# output: program stopped with signal 11.\n
+# output: program stopped with signal 11 (*).\n

; Check invalid access valid with --cris-900000xx.
; "PASS" area.
--- sim/testsuite/sim/cris/asm/movecpc.ms
+++ sim/testsuite/sim/cris/asm/movecpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register * PC is not implemented.\nprogram stopped with signal 5 (*).\n

# We deliberately match both "read from" and "write to" above.

--- sim/testsuite/sim/cris/asm/movempc.ms
+++ sim/testsuite/sim/cris/asm/movempc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/movepcb.ms
+++ sim/testsuite/sim/cris/asm/movepcb.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
startnostack
--- sim/testsuite/sim/cris/asm/movepcd.ms
+++ sim/testsuite/sim/cris/asm/movepcd.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register * PC is not implemented.\nprogram stopped with signal 5 (*).\n

# Both source and dest contain PC for "test.d r" (move.d r,r). Ideally,
# the output message should say "read" of PC, but we allow PC as source in
--- sim/testsuite/sim/cris/asm/movepcw.ms
+++ sim/testsuite/sim/cris/asm/movepcw.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
startnostack
--- sim/testsuite/sim/cris/asm/moveqpc.ms
+++ sim/testsuite/sim/cris/asm/moveqpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
startnostack
--- sim/testsuite/sim/cris/asm/moverbpc.ms
+++ sim/testsuite/sim/cris/asm/moverbpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
startnostack
--- sim/testsuite/sim/cris/asm/moverdpc.ms
+++ sim/testsuite/sim/cris/asm/moverdpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
startnostack
--- sim/testsuite/sim/cris/asm/moverpcb.ms
+++ sim/testsuite/sim/cris/asm/moverpcb.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
startnostack
--- sim/testsuite/sim/cris/asm/moverpcw.ms
+++ sim/testsuite/sim/cris/asm/moverpcw.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
startnostack
--- sim/testsuite/sim/cris/asm/moverwpc.ms
+++ sim/testsuite/sim/cris/asm/moverwpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
startnostack
--- sim/testsuite/sim/cris/asm/movppc.ms
+++ sim/testsuite/sim/cris/asm/movppc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/movrss.ms
+++ sim/testsuite/sim/cris/asm/movrss.ms
@@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
-# output: Write to support register is unimplemented\nprogram stopped with signal 5.\n
+# output: Write to support register is unimplemented\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/movscpc.ms
+++ sim/testsuite/sim/cris/asm/movscpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/movsmpc.ms
+++ sim/testsuite/sim/cris/asm/movsmpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/movsrpc.ms
+++ sim/testsuite/sim/cris/asm/movsrpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/movssr.ms
+++ sim/testsuite/sim/cris/asm/movssr.ms
@@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
-# output: Read of support register is unimplemented\nprogram stopped with signal 5.\n
+# output: Read of support register is unimplemented\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/movucpc.ms
+++ sim/testsuite/sim/cris/asm/movucpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/movumpc.ms
+++ sim/testsuite/sim/cris/asm/movumpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/movurpc.ms
+++ sim/testsuite/sim/cris/asm/movurpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/msteppc1.ms
+++ sim/testsuite/sim/cris/asm/msteppc1.ms
@@ -1,7 +1,7 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\n
-# output: program stopped with signal 5.\n
+# output: program stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/msteppc2.ms
+++ sim/testsuite/sim/cris/asm/msteppc2.ms
@@ -1,7 +1,7 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\n
-# output: program stopped with signal 5.\n
+# output: program stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/msteppc3.ms
+++ sim/testsuite/sim/cris/asm/msteppc3.ms
@@ -1,7 +1,7 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\n
-# output: program stopped with signal 5.\n
+# output: program stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/rfg.ms
+++ sim/testsuite/sim/cris/asm/rfg.ms
@@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
-# output: RFG isn't implemented\nprogram stopped with signal 5.\n
+# output: RFG isn't implemented\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/sbfs.ms
+++ sim/testsuite/sim/cris/asm/sbfs.ms
@@ -1,6 +1,6 @@
# mach: crisv10
# xerror:
-# output: SBFS isn't implemented\nprogram stopped with signal 5.\n
+# output: SBFS isn't implemented\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start
--- sim/testsuite/sim/cris/asm/subqpc.ms
+++ sim/testsuite/sim/cris/asm/subqpc.ms
@@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
-# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
+# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n

.include "testutils.inc"
start