From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 16132 invoked by alias); 19 Mar 2012 17:23:08 -0000 Received: (qmail 16119 invoked by uid 22791); 19 Mar 2012 17:23:06 -0000 X-SWARE-Spam-Status: No, hits=-4.6 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_HI,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from smtp.gentoo.org (HELO smtp.gentoo.org) (140.211.166.183) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 19 Mar 2012 17:22:41 +0000 Received: from vapier.localnet (localhost [127.0.0.1]) by smtp.gentoo.org (Postfix) with ESMTP id 9BDC51B4035; Mon, 19 Mar 2012 17:22:40 +0000 (UTC) From: Mike Frysinger To: "Hans-Peter Nilsson" Subject: Re: Please fix regressions from your sim changes Date: Mon, 19 Mar 2012 17:23:00 -0000 User-Agent: KMail/1.13.7 (Linux/3.2.0; KDE/4.6.5; x86_64; ; ) Cc: gdb-patches@sourceware.org References: <201203190628.q2J6SnLJ011314@ignucius.se.axis.com> In-Reply-To: <201203190628.q2J6SnLJ011314@ignucius.se.axis.com> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart7015795.HZtoK4PNDJ"; protocol="application/pgp-signature"; micalg=pgp-sha1 Content-Transfer-Encoding: 7bit Message-Id: <201203191322.40953.vapier@gentoo.org> X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-03/txt/msg00713.txt.bz2 --nextPart7015795.HZtoK4PNDJ Content-Type: multipart/mixed; boundary="Boundary-01=_gt2ZPb280LA+lMx" Content-Transfer-Encoding: 7bit --Boundary-01=_gt2ZPb280LA+lMx Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Content-length: 1097 On Monday 19 March 2012 02:28:49 Hans-Peter Nilsson wrote: > For mips-elf, there's just mips-elf is passing for me > From sim.log it seems just some expected patterns need updating. >=20 > Executing on host: mips-elf-ld hilo-hazard-1.s.o -N -Ttext=3D0x80010000 = -o > hilo-hazard-1.s.x (timeout =3D 300) > /tmp/hpautotest-sim/mips-elf/sim/mips/run hilo-hazard-1.s.x > HILO: MULT: OP at 0x80010048 too close to MF at 0x80010044 >=20 > output: HILO: MULT: OP at 0x80010048 too close to MF at 0x80010044 >=20 >=20 > pattern: HILO: * too close to MF at *\ > \ > program stopped*\ >=20 > FAIL: mips1 hilo-hazard-1.s (execution) the glob should eat the new signal string > For cris-elf, there's quite a bit more, three variants AFAICT; > three "signals" lost. patch attached should fix that > And really, why removing the "program stopped with signal" > common part? I see no reason to not just adding it back. it wasn't removed. the signal is now additionally being decoded. before: program stopped with signal 5. after: program stopped with signal 5 (Trace/breakpoint trap). -mike --Boundary-01=_gt2ZPb280LA+lMx Content-Type: text/x-patch; charset="UTF-8"; name="sim-cris-testsuite.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="sim-cris-testsuite.patch" Content-length: 13335 --- sim/testsuite/sim/cris/asm/addqpc.ms +++ sim/testsuite/sim/cris/asm/addqpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror: -# output: General register read of PC is not implemented.\nprogram stopped= with signal 5.\n +# output: General register read of PC is not implemented.\nprogram stopped= with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/boundmv32.ms +++ sim/testsuite/sim/cris/asm/boundmv32.ms @@ -1,6 +1,6 @@ # mach: crisv32 # xerror: -# output: program stopped with signal 4.\n +# output: program stopped with signal 4 (*).\n .include "testutils.inc" =20 ; Check that bound with a memory operand is invalid. --- sim/testsuite/sim/cris/asm/fidxd.ms +++ sim/testsuite/sim/cris/asm/fidxd.ms @@ -1,6 +1,6 @@ # mach: crisv32 # xerror: -# output: FIDXD isn't implemented\nprogram stopped with signal 5.\n +# output: FIDXD isn't implemented\nprogram stopped with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/fidxi.ms +++ sim/testsuite/sim/cris/asm/fidxi.ms @@ -1,6 +1,6 @@ # mach: crisv32 # xerror: -# output: FIDXI isn't implemented\nprogram stopped with signal 5.\n +# output: FIDXI isn't implemented\nprogram stopped with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/ftagd.ms +++ sim/testsuite/sim/cris/asm/ftagd.ms @@ -1,6 +1,6 @@ # mach: crisv32 # xerror: -# output: FTAGD isn't implemented\nprogram stopped with signal 5.\n +# output: FTAGD isn't implemented\nprogram stopped with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/ftagi.ms +++ sim/testsuite/sim/cris/asm/ftagi.ms @@ -1,6 +1,6 @@ # mach: crisv32 # xerror: -# output: FTAGI isn't implemented\nprogram stopped with signal 5.\n +# output: FTAGI isn't implemented\nprogram stopped with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/halt.ms +++ sim/testsuite/sim/cris/asm/halt.ms @@ -1,6 +1,6 @@ # mach: crisv32 # xerror: -# output: HALT isn't implemented\nprogram stopped with signal 5.\n +# output: HALT isn't implemented\nprogram stopped with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/io6.ms +++ sim/testsuite/sim/cris/asm/io6.ms @@ -4,7 +4,7 @@ # xerror: # output: b1e\n # output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n -# output: program stopped with signal 11.\n +# output: program stopped with signal 11 (*).\n =20 ; Check that invalid access to the simulator area is recognized. ; "FAIL" area. --- sim/testsuite/sim/cris/asm/io7.ms +++ sim/testsuite/sim/cris/asm/io7.ms @@ -4,7 +4,7 @@ # xerror: # output: ce11d0c\n # output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n -# output: program stopped with signal 11.\n +# output: program stopped with signal 11 (*).\n =20 ; Check that invalid access to the simulator area is recognized. ; "PASS" area. --- sim/testsuite/sim/cris/asm/io8.ms +++ sim/testsuite/sim/cris/asm/io8.ms @@ -3,7 +3,7 @@ # xerror: # output: b1e\n # output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n -# output: program stopped with signal 11.\n +# output: program stopped with signal 11 (*).\n =20 ; Check invalid access valid with --cris-900000xx. ; "FAIL" area. --- sim/testsuite/sim/cris/asm/io9.ms +++ sim/testsuite/sim/cris/asm/io9.ms @@ -3,7 +3,7 @@ # xerror: # output: ce11d0c\n # output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n -# output: program stopped with signal 11.\n +# output: program stopped with signal 11 (*).\n =20 ; Check invalid access valid with --cris-900000xx. ; "PASS" area. --- sim/testsuite/sim/cris/asm/movecpc.ms +++ sim/testsuite/sim/cris/asm/movecpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror: -# output: General register * PC is not implemented.\nprogram stopped with = signal 5.\n +# output: General register * PC is not implemented.\nprogram stopped with = signal 5 (*).\n =20 # We deliberately match both "read from" and "write to" above. =20 --- sim/testsuite/sim/cris/asm/movempc.ms +++ sim/testsuite/sim/cris/asm/movempc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror: -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/movepcb.ms +++ sim/testsuite/sim/cris/asm/movepcb.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register read of PC is not implemented.\nprogram stopped= with signal 5.\n +# output: General register read of PC is not implemented.\nprogram stopped= with signal 5 (*).\n =20 .include "testutils.inc" startnostack --- sim/testsuite/sim/cris/asm/movepcd.ms +++ sim/testsuite/sim/cris/asm/movepcd.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register * PC is not implemented.\nprogram stopped with = signal 5.\n +# output: General register * PC is not implemented.\nprogram stopped with = signal 5 (*).\n =20 # Both source and dest contain PC for "test.d r" (move.d r,r). Ideally, # the output message should say "read" of PC, but we allow PC as source in --- sim/testsuite/sim/cris/asm/movepcw.ms +++ sim/testsuite/sim/cris/asm/movepcw.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register read of PC is not implemented.\nprogram stopped= with signal 5.\n +# output: General register read of PC is not implemented.\nprogram stopped= with signal 5 (*).\n =20 .include "testutils.inc" startnostack --- sim/testsuite/sim/cris/asm/moveqpc.ms +++ sim/testsuite/sim/cris/asm/moveqpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" startnostack --- sim/testsuite/sim/cris/asm/moverbpc.ms +++ sim/testsuite/sim/cris/asm/moverbpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" startnostack --- sim/testsuite/sim/cris/asm/moverdpc.ms +++ sim/testsuite/sim/cris/asm/moverdpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" startnostack --- sim/testsuite/sim/cris/asm/moverpcb.ms +++ sim/testsuite/sim/cris/asm/moverpcb.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register read of PC is not implemented.\nprogram stopped= with signal 5.\n +# output: General register read of PC is not implemented.\nprogram stopped= with signal 5 (*).\n =20 .include "testutils.inc" startnostack --- sim/testsuite/sim/cris/asm/moverpcw.ms +++ sim/testsuite/sim/cris/asm/moverpcw.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register read of PC is not implemented.\nprogram stopped= with signal 5.\n +# output: General register read of PC is not implemented.\nprogram stopped= with signal 5 (*).\n =20 .include "testutils.inc" startnostack --- sim/testsuite/sim/cris/asm/moverwpc.ms +++ sim/testsuite/sim/cris/asm/moverwpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" startnostack --- sim/testsuite/sim/cris/asm/movppc.ms +++ sim/testsuite/sim/cris/asm/movppc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror: -# output: General register read of PC is not implemented.\nprogram stopped= with signal 5.\n +# output: General register read of PC is not implemented.\nprogram stopped= with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/movrss.ms +++ sim/testsuite/sim/cris/asm/movrss.ms @@ -1,6 +1,6 @@ # mach: crisv32 # xerror: -# output: Write to support register is unimplemented\nprogram stopped with= signal 5.\n +# output: Write to support register is unimplemented\nprogram stopped with= signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/movscpc.ms +++ sim/testsuite/sim/cris/asm/movscpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror: -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/movsmpc.ms +++ sim/testsuite/sim/cris/asm/movsmpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror: -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/movsrpc.ms +++ sim/testsuite/sim/cris/asm/movsrpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/movssr.ms +++ sim/testsuite/sim/cris/asm/movssr.ms @@ -1,6 +1,6 @@ # mach: crisv32 # xerror: -# output: Read of support register is unimplemented\nprogram stopped with = signal 5.\n +# output: Read of support register is unimplemented\nprogram stopped with = signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/movucpc.ms +++ sim/testsuite/sim/cris/asm/movucpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror: -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/movumpc.ms +++ sim/testsuite/sim/cris/asm/movumpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror: -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/movurpc.ms +++ sim/testsuite/sim/cris/asm/movurpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror:=20 -# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5.\n +# output: General register write to PC is not implemented.\nprogram stoppe= d with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/msteppc1.ms +++ sim/testsuite/sim/cris/asm/msteppc1.ms @@ -1,7 +1,7 @@ # mach: crisv3 crisv8 crisv10 # xerror: # output: General register read of PC is not implemented.\n -# output: program stopped with signal 5.\n +# output: program stopped with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/msteppc2.ms +++ sim/testsuite/sim/cris/asm/msteppc2.ms @@ -1,7 +1,7 @@ # mach: crisv3 crisv8 crisv10 # xerror: # output: General register read of PC is not implemented.\n -# output: program stopped with signal 5.\n +# output: program stopped with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/msteppc3.ms +++ sim/testsuite/sim/cris/asm/msteppc3.ms @@ -1,7 +1,7 @@ # mach: crisv3 crisv8 crisv10 # xerror: # output: General register read of PC is not implemented.\n -# output: program stopped with signal 5.\n +# output: program stopped with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/rfg.ms +++ sim/testsuite/sim/cris/asm/rfg.ms @@ -1,6 +1,6 @@ # mach: crisv32 # xerror: -# output: RFG isn't implemented\nprogram stopped with signal 5.\n +# output: RFG isn't implemented\nprogram stopped with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/sbfs.ms +++ sim/testsuite/sim/cris/asm/sbfs.ms @@ -1,6 +1,6 @@ # mach: crisv10 # xerror: -# output: SBFS isn't implemented\nprogram stopped with signal 5.\n +# output: SBFS isn't implemented\nprogram stopped with signal 5 (*).\n =20 .include "testutils.inc" start --- sim/testsuite/sim/cris/asm/subqpc.ms +++ sim/testsuite/sim/cris/asm/subqpc.ms @@ -1,6 +1,6 @@ # mach: crisv3 crisv8 crisv10 # xerror: -# output: General register read of PC is not implemented.\nprogram stopped= with signal 5.\n +# output: General register read of PC is not implemented.\nprogram stopped= with signal 5 (*).\n =20 .include "testutils.inc" start --Boundary-01=_gt2ZPb280LA+lMx-- --nextPart7015795.HZtoK4PNDJ Content-Type: application/pgp-signature; name=signature.asc Content-Description: This is a digitally signed message part. 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