From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14952 invoked by alias); 10 Feb 2012 00:16:11 -0000 Received: (qmail 14839 invoked by uid 22791); 10 Feb 2012 00:15:58 -0000 X-SWARE-Spam-Status: No, hits=-6.7 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_HI,SPF_HELO_PASS,TW_EG,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 10 Feb 2012 00:15:39 +0000 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q1A0FdNx021656 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Thu, 9 Feb 2012 19:15:39 -0500 Received: from mesquite.lan ([10.3.113.11]) by int-mx12.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q1A0Fckk031886 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES128-SHA bits=128 verify=NO) for ; Thu, 9 Feb 2012 19:15:38 -0500 Date: Fri, 10 Feb 2012 00:16:00 -0000 From: Kevin Buettner To: gdb-patches@sourceware.org Subject: [RFC] rl78: Rearrange order in which registers are displayed Message-ID: <20120209171537.20c1c6b1@mesquite.lan> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2012-02/txt/msg00166.txt.bz2 The patch below uses register groups to shorten the list of registers displayed when "info registers" is used. It adds some pseudo registers and rearranges others so that the banked registers are displayed at the end for "info all-registers". The register order from 0 to NREGS stays the same. This change was requested by Renesas. They wanted the more useful and important registers displayed earlier on for "info all-registers". I considered writing a custom method for printing registers, but it seems that this approach has fallen out of favor these days. Also, I would guess that the custom approach might not be compatible with MI enabled clients. Comments? * rl78-tdep.c (reggroups.h): Include. (RL78_RAW_BANK0_R0_REGNUM, RL78_RAW_BANK0_R1_REGNUM) (RL78_RAW_BANK0_R2_REGNUM, RL78_RAW_BANK0_R3_REGNUM) (RL78_RAW_BANK0_R4_REGNUM, RL78_RAW_BANK0_R5_REGNUM) (RL78_RAW_BANK0_R6_REGNUM, RL78_RAW_BANK0_R7_REGNUM) (RL78_RAW_BANK1_R0_REGNUM, RL78_RAW_BANK1_R1_REGNUM) (RL78_RAW_BANK1_R2_REGNUM, RL78_RAW_BANK1_R3_REGNUM) (RL78_RAW_BANK1_R4_REGNUM, RL78_RAW_BANK1_R5_REGNUM) (RL78_RAW_BANK1_R6_REGNUM, RL78_RAW_BANK1_R7_REGNUM) (RL78_RAW_BANK2_R0_REGNUM, RL78_RAW_BANK2_R1_REGNUM) (RL78_RAW_BANK2_R2_REGNUM, RL78_RAW_BANK2_R3_REGNUM) (RL78_RAW_BANK2_R4_REGNUM, RL78_RAW_BANK2_R5_REGNUM) (RL78_RAW_BANK2_R6_REGNUM, RL78_RAW_BANK2_R7_REGNUM) (RL78_RAW_BANK3_R0_REGNUM, RL78_RAW_BANK3_R1_REGNUM) (RL78_RAW_BANK3_R2_REGNUM, RL78_RAW_BANK3_R3_REGNUM) (RL78_RAW_BANK3_R4_REGNUM, RL78_RAW_BANK3_R5_REGNUM) (RL78_RAW_BANK3_R6_REGNUM, RL78_RAW_BANK3_R7_REGNUM): Add to beginning of register list. (RL78_BANK0_R0_REGNUM, RL78_BANK0_R1_REGNUM, RL78_BANK0_R2_REGNUM) (RL78_BANK0_R3_REGNUM, RL78_BANK0_R4_REGNUM, RL78_BANK0_R5_REGNUM) (RL78_BANK0_R6_REGNUM, RL78_BANK0_R7_REGNUM, RL78_BANK1_R0_REGNUM) (RL78_BANK1_R1_REGNUM, RL78_BANK1_R2_REGNUM, RL78_BANK1_R3_REGNUM) (RL78_BANK1_R4_REGNUM, RL78_BANK1_R5_REGNUM, RL78_BANK1_R6_REGNUM) (RL78_BANK1_R7_REGNUM, RL78_BANK2_R0_REGNUM, RL78_BANK2_R1_REGNUM) (RL78_BANK2_R2_REGNUM, RL78_BANK2_R3_REGNUM, RL78_BANK2_R4_REGNUM) (RL78_BANK2_R5_REGNUM, RL78_BANK2_R6_REGNUM, RL78_BANK2_R7_REGNUM) (RL78_BANK3_R0_REGNUM, RL78_BANK3_R1_REGNUM, RL78_BANK3_R2_REGNUM) (RL78_BANK3_R3_REGNUM, RL78_BANK3_R4_REGNUM, RL78_BANK3_R5_REGNUM) (RL78_BANK3_R6_REGNUM, RL78_BANK3_R7_REGNUM): Move these into the pseudo registers. Rearrange other pseudo registers too so that the bank registers appear at the end. (rl78_register_type): Account for the fact that the byte sized bank registers are now pseudo-registers. (rl78_register_name): Rearrange the register name array. Make initial set of raw banked registers inaccessible. (rl78_register_reggroup_p, rl78_register_sim_regno): New functions. (rl78_pseudo_register_read, rl78_pseudo_register_write): Add case for copying bytes back and forth between raw and pseudo versions of the banked registers. Update other cases to reflect the changed names. (rl78_return_value): Update to account for changed names of raw registers. (rl78_gdbarch_init): Register rl78_register_reggroup_p() and rl78_register_sim_regno(). Index: rl78-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/rl78-tdep.c,v retrieving revision 1.1 diff -u -p -r1.1 rl78-tdep.c --- rl78-tdep.c 4 Feb 2012 06:05:50 -0000 1.1 +++ rl78-tdep.c 9 Feb 2012 21:06:37 -0000 @@ -33,6 +33,7 @@ #include "value.h" #include "gdbcore.h" #include "dwarf2-frame.h" +#include "reggroups.h" #include "elf/rl78.h" #include "elf-bfd.h" @@ -54,7 +55,73 @@ enum enum { /* All general purpose registers are 8 bits wide. */ - RL78_BANK0_R0_REGNUM = 0, + RL78_RAW_BANK0_R0_REGNUM = 0, + RL78_RAW_BANK0_R1_REGNUM, + RL78_RAW_BANK0_R2_REGNUM, + RL78_RAW_BANK0_R3_REGNUM, + RL78_RAW_BANK0_R4_REGNUM, + RL78_RAW_BANK0_R5_REGNUM, + RL78_RAW_BANK0_R6_REGNUM, + RL78_RAW_BANK0_R7_REGNUM, + + RL78_RAW_BANK1_R0_REGNUM, + RL78_RAW_BANK1_R1_REGNUM, + RL78_RAW_BANK1_R2_REGNUM, + RL78_RAW_BANK1_R3_REGNUM, + RL78_RAW_BANK1_R4_REGNUM, + RL78_RAW_BANK1_R5_REGNUM, + RL78_RAW_BANK1_R6_REGNUM, + RL78_RAW_BANK1_R7_REGNUM, + + RL78_RAW_BANK2_R0_REGNUM, + RL78_RAW_BANK2_R1_REGNUM, + RL78_RAW_BANK2_R2_REGNUM, + RL78_RAW_BANK2_R3_REGNUM, + RL78_RAW_BANK2_R4_REGNUM, + RL78_RAW_BANK2_R5_REGNUM, + RL78_RAW_BANK2_R6_REGNUM, + RL78_RAW_BANK2_R7_REGNUM, + + RL78_RAW_BANK3_R0_REGNUM, + RL78_RAW_BANK3_R1_REGNUM, + RL78_RAW_BANK3_R2_REGNUM, + RL78_RAW_BANK3_R3_REGNUM, + RL78_RAW_BANK3_R4_REGNUM, + RL78_RAW_BANK3_R5_REGNUM, + RL78_RAW_BANK3_R6_REGNUM, + RL78_RAW_BANK3_R7_REGNUM, + + RL78_PSW_REGNUM, /* 8 bits */ + RL78_ES_REGNUM, /* 8 bits */ + RL78_CS_REGNUM, /* 8 bits */ + RL78_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */ + + /* Fixed address SFRs (some of those above are SFRs too.) */ + RL78_SPL_REGNUM, /* 8 bits; lower half of SP */ + RL78_SPH_REGNUM, /* 8 bits; upper half of SP */ + RL78_PMC_REGNUM, /* 8 bits */ + RL78_MEM_REGNUM, /* 8 bits ?? */ + + RL78_NUM_REGS, + + /* Pseudo registers. */ + RL78_SP_REGNUM = RL78_NUM_REGS, + + RL78_X_REGNUM, + RL78_A_REGNUM, + RL78_C_REGNUM, + RL78_B_REGNUM, + RL78_E_REGNUM, + RL78_D_REGNUM, + RL78_L_REGNUM, + RL78_H_REGNUM, + + RL78_AX_REGNUM, + RL78_BC_REGNUM, + RL78_DE_REGNUM, + RL78_HL_REGNUM, + + RL78_BANK0_R0_REGNUM, RL78_BANK0_R1_REGNUM, RL78_BANK0_R2_REGNUM, RL78_BANK0_R3_REGNUM, @@ -90,21 +157,7 @@ enum RL78_BANK3_R6_REGNUM, RL78_BANK3_R7_REGNUM, - RL78_PSW_REGNUM, /* 8 bits */ - RL78_ES_REGNUM, /* 8 bits */ - RL78_CS_REGNUM, /* 8 bits */ - RL78_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */ - - /* Fixed address SFRs (some of those above are SFRs too.) */ - RL78_SPL_REGNUM, /* 8 bits; lower half of SP */ - RL78_SPH_REGNUM, /* 8 bits; upper half of SP */ - RL78_PMC_REGNUM, /* 8 bits */ - RL78_MEM_REGNUM, /* 8 bits ?? */ - - RL78_NUM_REGS, - - /* Pseudo registers. */ - RL78_BANK0_RP0_REGNUM = RL78_NUM_REGS, + RL78_BANK0_RP0_REGNUM, RL78_BANK0_RP1_REGNUM, RL78_BANK0_RP2_REGNUM, RL78_BANK0_RP3_REGNUM, @@ -124,21 +177,6 @@ enum RL78_BANK3_RP2_REGNUM, RL78_BANK3_RP3_REGNUM, - RL78_SP_REGNUM, - - RL78_X_REGNUM, - RL78_A_REGNUM, - RL78_C_REGNUM, - RL78_B_REGNUM, - RL78_E_REGNUM, - RL78_D_REGNUM, - RL78_L_REGNUM, - RL78_H_REGNUM, - - RL78_AX_REGNUM, - RL78_BC_REGNUM, - RL78_DE_REGNUM, - RL78_HL_REGNUM, RL78_NUM_TOTAL_REGS, RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS }; @@ -206,7 +244,9 @@ rl78_register_type (struct gdbarch *gdba if (reg_nr == RL78_PC_REGNUM) return tdep->rl78_code_pointer; else if (reg_nr <= RL78_MEM_REGNUM - || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)) + || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM) + || (RL78_BANK0_R0_REGNUM <= reg_nr + && reg_nr <= RL78_BANK3_R7_REGNUM)) return tdep->rl78_int8; else return tdep->rl78_data_pointer; @@ -219,6 +259,68 @@ rl78_register_name (struct gdbarch *gdba { static const char *const reg_names[] = { + "", /* bank0_r0 */ + "", /* bank0_r1 */ + "", /* bank0_r2 */ + "", /* bank0_r3 */ + "", /* bank0_r4 */ + "", /* bank0_r5 */ + "", /* bank0_r6 */ + "", /* bank0_r7 */ + + "", /* bank1_r0 */ + "", /* bank1_r1 */ + "", /* bank1_r2 */ + "", /* bank1_r3 */ + "", /* bank1_r4 */ + "", /* bank1_r5 */ + "", /* bank1_r6 */ + "", /* bank1_r7 */ + + "", /* bank2_r0 */ + "", /* bank2_r1 */ + "", /* bank2_r2 */ + "", /* bank2_r3 */ + "", /* bank2_r4 */ + "", /* bank2_r5 */ + "", /* bank2_r6 */ + "", /* bank2_r7 */ + + "", /* bank3_r0 */ + "", /* bank3_r1 */ + "", /* bank3_r2 */ + "", /* bank3_r3 */ + "", /* bank3_r4 */ + "", /* bank3_r5 */ + "", /* bank3_r6 */ + "", /* bank3_r7 */ + + "psw", + "es", + "cs", + "pc", + + "", /* spl */ + "", /* sph */ + "pmc", + "mem", + + "sp", + + "x", + "a", + "c", + "b", + "e", + "d", + "l", + "h", + + "ax", + "bc", + "de", + "hl", + "bank0_r0", "bank0_r1", "bank0_r2", @@ -255,16 +357,6 @@ rl78_register_name (struct gdbarch *gdba "bank3_r6", "bank3_r7", - "psw", - "es", - "cs", - "pc", - - "spl", - "sph", - "pmc", - "mem", - "bank0_rp0", "bank0_rp1", "bank0_rp2", @@ -283,26 +375,41 @@ rl78_register_name (struct gdbarch *gdba "bank3_rp0", "bank3_rp1", "bank3_rp2", - "bank3_rp3", + "bank3_rp3" + }; - "sp", + return reg_names[regnr]; +} - "x", - "a", - "c", - "b", - "e", - "d", - "l", - "h", +/* Implement the "register_reggroup_p" gdbarch method. */ - "ax", - "bc", - "de", - "hl" - }; +static int +rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum, + struct reggroup *group) +{ + if (group == all_reggroup) + return 1; - return reg_names[regnr]; + /* All other registers are saved and restored. */ + if (group == save_reggroup || group == restore_reggroup) + { + if (regnum < RL78_NUM_REGS) + return 1; + else + return 0; + } + + if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM) + || regnum == RL78_ES_REGNUM + || regnum == RL78_CS_REGNUM + || regnum == RL78_SPL_REGNUM + || regnum == RL78_SPH_REGNUM + || regnum == RL78_PMC_REGNUM + || regnum == RL78_MEM_REGNUM + || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM)) + return group == system_reggroup; + + return group == general_reggroup; } /* Strip bits to form an instruction address. (When fetching a @@ -332,10 +439,17 @@ rl78_pseudo_register_read (struct gdbarc { enum register_status status; - if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM) + if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM) + { + int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + + (reg - RL78_BANK0_R0_REGNUM); + + status = regcache_raw_read (regcache, raw_regnum, buffer); + } + else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM) { int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM) - + RL78_BANK0_R0_REGNUM; + + RL78_RAW_BANK0_R0_REGNUM; status = regcache_raw_read (regcache, raw_regnum, buffer); if (status == REG_VALID) @@ -356,7 +470,7 @@ rl78_pseudo_register_read (struct gdbarc { /* RSB0 is at bit 3; RSBS1 is at bit 5. */ int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); - int raw_regnum = RL78_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK + int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK + (reg - RL78_X_REGNUM); status = regcache_raw_read (regcache, raw_regnum, buffer); } @@ -370,7 +484,7 @@ rl78_pseudo_register_read (struct gdbarc { /* RSB0 is at bit 3; RSBS1 is at bit 5. */ int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); - int raw_regnum = RL78_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK + int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK + 2 * (reg - RL78_AX_REGNUM); status = regcache_raw_read (regcache, raw_regnum, buffer); if (status == REG_VALID) @@ -390,10 +504,17 @@ rl78_pseudo_register_write (struct gdbar struct regcache *regcache, int reg, const gdb_byte *buffer) { - if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM) + if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM) + { + int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + + (reg - RL78_BANK0_R0_REGNUM); + + regcache_raw_write (regcache, raw_regnum, buffer); + } + else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM) { int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM) - + RL78_BANK0_R0_REGNUM; + + RL78_RAW_BANK0_R0_REGNUM; regcache_raw_write (regcache, raw_regnum, buffer); regcache_raw_write (regcache, raw_regnum + 1, buffer + 1); @@ -412,7 +533,7 @@ rl78_pseudo_register_write (struct gdbar regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw); bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); /* RSB0 is at bit 3; RSBS1 is at bit 5. */ - raw_regnum = RL78_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK + raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK + (reg - RL78_X_REGNUM); regcache_raw_write (regcache, raw_regnum, buffer); } @@ -424,7 +545,7 @@ rl78_pseudo_register_write (struct gdbar regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw); bank = ((psw >> 3) & 1) | ((psw >> 4) & 1); /* RSB0 is at bit 3; RSBS1 is at bit 5. */ - raw_regnum = RL78_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK + raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK + 2 * (reg - RL78_AX_REGNUM); regcache_raw_write (regcache, raw_regnum, buffer); regcache_raw_write (regcache, raw_regnum + 1, buffer + 1); @@ -796,6 +917,19 @@ rl78_dwarf_reg_to_regnum (struct gdbarch reg); } +/* Implement the `register_sim_regno' gdbarch method. */ + +static int +rl78_register_sim_regno(struct gdbarch *gdbarch, int regnum) +{ + gdb_assert (regnum < RL78_NUM_REGS); + + /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We + just want to override the default here which disallows register + numbers which have no names. */ + return regnum; +} + /* Implement the "return_value" gdbarch method. */ static enum return_value_convention @@ -814,7 +948,7 @@ rl78_return_value (struct gdbarch *gdbar if (readbuf) { ULONGEST u; - int argreg = RL78_BANK1_R0_REGNUM; + int argreg = RL78_RAW_BANK1_R0_REGNUM; int offset = 0; while (valtype_len > 0) @@ -830,7 +964,7 @@ rl78_return_value (struct gdbarch *gdbar if (writebuf) { ULONGEST u; - int argreg = RL78_BANK1_R0_REGNUM; + int argreg = RL78_RAW_BANK1_R0_REGNUM; int offset = 0; while (valtype_len > 0) @@ -981,6 +1115,8 @@ rl78_gdbarch_init (struct gdbarch_info i set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read); set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write); set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum); + set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p); + set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno); /* Data types. */ set_gdbarch_char_signed (gdbarch, 0);