From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 10085 invoked by alias); 27 May 2011 22:11:30 -0000 Received: (qmail 10075 invoked by uid 22791); 27 May 2011 22:11:29 -0000 X-SWARE-Spam-Status: No, hits=-1.7 required=5.0 tests=AWL,BAYES_00,MSGID_FROM_MTA_HEADER,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mtagate3.uk.ibm.com (HELO mtagate3.uk.ibm.com) (194.196.100.163) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 27 May 2011 22:11:15 +0000 Received: from d06nrmr1507.portsmouth.uk.ibm.com (d06nrmr1507.portsmouth.uk.ibm.com [9.149.38.233]) by mtagate3.uk.ibm.com (8.13.1/8.13.1) with ESMTP id p4RMB5wB031507 for ; Fri, 27 May 2011 22:11:05 GMT Received: from d06av02.portsmouth.uk.ibm.com (d06av02.portsmouth.uk.ibm.com [9.149.37.228]) by d06nrmr1507.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id p4RMB5u31597498 for ; Fri, 27 May 2011 23:11:05 +0100 Received: from d06av02.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id p4RMB5U2003691 for ; Fri, 27 May 2011 16:11:05 -0600 Received: from tuxmaker.boeblingen.de.ibm.com (tuxmaker.boeblingen.de.ibm.com [9.152.85.9]) by d06av02.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with SMTP id p4RMB49s003688; Fri, 27 May 2011 16:11:04 -0600 Message-Id: <201105272211.p4RMB49s003688@d06av02.portsmouth.uk.ibm.com> Received: by tuxmaker.boeblingen.de.ibm.com (sSMTP sendmail emulation); Sat, 28 May 2011 00:11:04 +0200 Subject: Re: [try 2nd 5/8] Displaced stepping for Thumb 32-bit insns To: yao@codesourcery.com (Yao Qi) Date: Fri, 27 May 2011 22:11:00 -0000 From: "Ulrich Weigand" Cc: gdb-patches@sourceware.org In-Reply-To: <4DDA45BA.5050400@codesourcery.com> from "Yao Qi" at May 23, 2011 07:32:10 PM MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2011-05/txt/msg00659.txt.bz2 Yao Qi wrote: > On 05/18/2011 01:14 AM, Ulrich Weigand wrote: > > In fact, unless I'm missing something, in Thumb mode no coprocessor > > instruction actually uses the PC (either RN == 15 indicates some other > > operation, or else it is specified as unpredictable). So those should > > simply all be copied unmodified ... > > I can understand almost of your comments except this one. I think you > are right, but there are still some cases that PC is used in this > category of instructions. > > thumb2_copy_copro_load_store covers instructions STC/STC2, VLDR/VSTR and > LDC/LDC2 (literal and immediate). I re-read ARM ARM again, and find that, > > STC/STC2 doesn't use PC. ARM ARM said "if n == 15 && (wback || > CurrentInstrSet() != InstrSet_ARM) then UNPREDICTABLE;" > > VSTR doesn't use PC. ARM ARM said "if n == 15 && CurrentInstrSet() != > InstrSet_ARM then UNPREDICTABLE;" > > However, LDC/LDC2/VLDR can use PC. > > VLDR{.32} , [PC, #+/-] > > LDC, LDC2 (literal or immediate) > LDC{L} ,,[PC],