From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23250 invoked by alias); 21 May 2011 19:20:09 -0000 Received: (qmail 23240 invoked by uid 22791); 21 May 2011 19:20:08 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=AWL,BAYES_00,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from sibelius.xs4all.nl (HELO glazunov.sibelius.xs4all.nl) (83.163.83.176) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 21 May 2011 19:19:54 +0000 Received: from glazunov.sibelius.xs4all.nl (kettenis@localhost [127.0.0.1]) by glazunov.sibelius.xs4all.nl (8.14.3/8.14.3) with ESMTP id p4LJJpUB004314 for ; Sat, 21 May 2011 21:19:51 +0200 (CEST) Received: (from kettenis@localhost) by glazunov.sibelius.xs4all.nl (8.14.3/8.14.3/Submit) id p4LJJn5Z013541; Sat, 21 May 2011 21:19:49 +0200 (CEST) Date: Sat, 21 May 2011 19:20:00 -0000 Message-Id: <201105211919.p4LJJn5Z013541@glazunov.sibelius.xs4all.nl> From: Mark Kettenis To: gdb-patches@sourceware.org Subject: [PATCH] %g0 on sparc should always be available Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2011-05/txt/msg00502.txt.bz2 Many RISC CPUs have a register that's hardwired to 0. Typically GDB code uses regcache_raw_supply(..., ..., NULL) to "transfer" the value of such a register. However these days, that marks the register as unavailable. This diff fixes that for %g0 on SPARC. Committed as obvious. 2011-05-21 Mark Kettenis * sparc-nat.c (sparc_fetch_inferior_registers): Explicitly supply zero as the value for %g0 in the register cache. * sparc-tdep.c (sparc32_supply_gregset): Likewise. * sparc64-tdep.c (sparc64_supply_gregset): Likewise. Index: sparc-nat.c =================================================================== RCS file: /cvs/src/src/gdb/sparc-nat.c,v retrieving revision 1.43 diff -u -p -r1.43 sparc-nat.c --- sparc-nat.c 1 Jan 2011 15:33:15 -0000 1.43 +++ sparc-nat.c 21 May 2011 19:08:34 -0000 @@ -159,7 +159,9 @@ sparc_fetch_inferior_registers (struct t if (regnum == SPARC_G0_REGNUM) { - regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); + gdb_byte zero[8] = { 0 }; + + regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); return; } Index: sparc-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/sparc-tdep.c,v retrieving revision 1.219 diff -u -p -r1.219 sparc-tdep.c --- sparc-tdep.c 18 Mar 2011 18:52:32 -0000 1.219 +++ sparc-tdep.c 21 May 2011 19:08:34 -0000 @@ -1618,6 +1618,7 @@ sparc32_supply_gregset (const struct spa int regnum, const void *gregs) { const gdb_byte *regs = gregs; + gdb_byte zero[4] = { 0 }; int i; if (regnum == SPARC32_PSR_REGNUM || regnum == -1) @@ -1637,7 +1638,7 @@ sparc32_supply_gregset (const struct spa regs + gregset->r_y_offset); if (regnum == SPARC_G0_REGNUM || regnum == -1) - regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); + regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) { Index: sparc64-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/sparc64-tdep.c,v retrieving revision 1.53 diff -u -p -r1.53 sparc64-tdep.c --- sparc64-tdep.c 18 Mar 2011 18:52:32 -0000 1.53 +++ sparc64-tdep.c 21 May 2011 19:08:35 -0000 @@ -1206,6 +1206,7 @@ sparc64_supply_gregset (const struct spa enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); int sparc32 = (gdbarch_ptr_bit (gdbarch) == 32); const gdb_byte *regs = gregs; + gdb_byte zero[8] = { 0 }; int i; if (sparc32) @@ -1268,7 +1269,7 @@ sparc64_supply_gregset (const struct spa } if (regnum == SPARC_G0_REGNUM || regnum == -1) - regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); + regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) {