[PATCH] opcodes m68k : fix disassembling movecr register names for v4e

[Philippe De Muyter <phdm@macqel.be>]

Hello all,

Some register names were missing in disassembling of the m68k movecr insn,
other used only the old names, not the v4e names.  Here is a fix.

Philippe

2009-08-15  Philippe De Muyter  <phdm@macqel.be>

	* m68k-dis.c (print_insn_arg): Add movecr register names for
	coldfire v4e families.

diff -r fc6f6bd61c7a opcodes/m68k-dis.c
--- a/opcodes/m68k-dis.c	Wed Aug 12 12:53:29 2009 +0200
+++ b/opcodes/m68k-dis.c	Sat Aug 15 23:45:11 2009 +0200
@@ -623,35 +623,59 @@ print_insn_arg (const char *d,
     case 'J':
       {
 	/* FIXME: There's a problem here, different m68k processors call the
-	   same address different names. This table can't get it right
-	   because it doesn't know which processor it's disassembling for.  */
-	static const struct { char *name; int value; } names[]
-	  = {{"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
+	   same address different names. The tables below try to get it right
+	   using info->mach, but only for v4e.  */
+	struct regname { char *name; int value; };
+	static const struct regname names[] = {
+	     {"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002},
 	     {"%tc",  0x003}, {"%itt0",0x004}, {"%itt1", 0x005},
              {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008},
 	     {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802},
 	     {"%msp", 0x803}, {"%isp", 0x804},
+	     {"%pc", 0x80f},
 	     /* reg c04 is sometimes called flashbar or rambar.
 		rec c05 is also sometimes called rambar.  */
 	     {"%rambar0", 0xc04}, {"%rambar1", 0xc05},
 
+	     {"%mbar", 0xc0f},
+
 	     /* Should we be calling this psr like we do in case 'Y'?  */
 	     {"%mmusr",0x805},
 
              {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808},
 
 	     /* Fido added these.  */
-             {"%cac", 0xffe}, {"%mbo", 0xfff}};
+             {"%cac", 0xffe}, {"%mbo", 0xfff}
+	};
+	/* alternate names for v4e (MCF5407/5445x/MCF547x/MCF548x), at least */
+	static const struct regname names_v4e[] = {
+	     {"%asid",0x003}, {"%acr0",0x004}, {"%acr1",0x005},
+	     {"%acr2",0x006}, {"%acr3",0x007}, {"%mmubar",0x008},
+	};
+	unsigned int arch_mask;
 
+	arch_mask = bfd_m68k_mach_to_features (info->mach);
+#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
 	val = fetch_arg (buffer, place, 12, info);
-	for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--)
+	if (arch_mask & (mcfisa_b|mcfisa_c))
+	  {
+	  for (regno = ARRAY_SIZE(names_v4e); --regno >= 0; )
+	    if (names_v4e[regno].value == val)
+	      {
+		(*info->fprintf_func) (info->stream, "%s", names_v4e[regno].name);
+		break;
+	      }
+	  if (regno >= 0)
+	    break;
+	  }
+	for (regno = ARRAY_SIZE(names) - 1; regno >= 0; regno--)
 	  if (names[regno].value == val)
 	    {
 	      (*info->fprintf_func) (info->stream, "%s", names[regno].name);
 	      break;
 	    }
 	if (regno < 0)
-	  (*info->fprintf_func) (info->stream, "%d", val);
+	  (*info->fprintf_func) (info->stream, "0x%x", val);
       }
       break;